Cisco Technology, Inc.

Sanjeev A Mahajan

Andrew McRae

David James Stewart

Venkaiah Dukkipati

A system and method for implementing a CPU/Network Device Interface that reduces the CPU involvement in managing the interface. New data structures in shared memory that are either read-only or write-only by CPU allow the CPU to efficiently utilize techniques such as write-posting and cache prefetching. Additionally, hardware-assisted packet transmission and high-level packet flow control reduce the burden on the CPU. A fair allocation system assures fair access to the receive interface by multiple line cards.

Network device/CPU interface scheme

A clock selection controller is shown which allows a user to assign a priority scheme to recovered clock signals obtained from communication facilities. The clock selection controller also receives a plurality of alarm signals corresponding to the communications facilities for each of the recovered clock signals. The clock selection controller then automatically selects, for output as a reference clock signal, the highest priority clock input available for which the corresponding alarm signals are inactive. In the absence of an available clock input in the priority scheme, the processor selects a free running clock input.

Growing community of inventors

Sunnyvale, CA, United States of America

Sanjeev A Mahajan