Cosmic Circuits Private Limited

Sanjeeb Kumar Ghosh

Prakash Easwaran

Prasenjit Bhowmik

Sundararajan Krishnan

Sumanth Chakkirala

Prasun Kali Bhattacharya

Chandrashekar Lakshminarayanan

Mukesh Khatri

Chakravarthy Srinivasan

Venkatesh Teeka Srinivasa Shetty

Srinivasan Chakravarthy

Venkatesh Teeka Srinvasa Setty

A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

System and method for reducing power dissipation in an analog to digital converter

A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

System and method for improving dynamic performance of a circuit

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Chandan-Pukur, India

Sanjeeb Kumar Ghosh