Mips Technologies, Inc.

Sun Microsystems, Inc.

Qualcomm Incorporated

Nband Communications

Sirf Technology, Inc.

Sanjay Vishin

Ryan C Kinter

Marc R Tremblay

James Michael O'Connor

Darren Miller Jones

Ralph Akram Gholmieh

Susheel Kumar Yadav Yadagiri

Guy Lewis Steele, Jr

Ole Agesen

Steven K Heller

Michael Gottlieb Jensen

Thomas Albert Petersen

Derek R White

Varun Tutpetkeshavamurthy

Min Wang

Sivaramakrishna Veerepalli

Vaibhav Kumar

Siddharth Chitnis

Gunes Aybay

Kevin D Kissell

Zahir Ebrahim

G Michael Uhler

Joseph A Petolino

Steve Gronemeyer

Bojun Pan

Adam Stoler

Russell W Bell

Systems, methods, and devices of the various embodiments provide for multipath transport of Internet Protocol (IP) packets by a computing device including a plurality of modems. In various embodiments, IP packets may be assigned to a selected one of a plurality of modems for transport based on available bandwidths of each of the plurality of modems.

Preferred path network scheduling in multi-modem setup

Systems, methods, and devices of the various embodiments provide a multipath communication scheduler for an in-vehicle computing device, such as a vehicle's autonomous driving system, vehicle's telematics unit, vehicle's control system, etc. In various embodiments, a centralized scheduler for an in-vehicle computing device may assign packets for transport to a plurality of modems based at least in part on delivery delays associated with the plurality of modems. In various embodiments, delivery delays may be determined based on one or more of queue sizes of the plurality of modems, delivery rate estimates of the plurality of modems, and end to end delay estimates.

Multi-modem scheduler for multimedia streams

Systems, methods, and devices of the various embodiments provide for multipath transport of Internet Protocol (IP) packets by an in-vehicle computing device, such as a vehicle's autonomous driving system, vehicle's telematics unit, vehicle's control system, etc. In various embodiments, IP packets may be extended to include tracking information. In various embodiments, the tracking information may include sequence numbers, sender reports, receiver reports, version indications, and/or length indications. In various embodiments, IP packets may be extended to include tracking information by a centralized scheduler for an in-vehicle computing device including a plurality of modems and/or a destination computing device.

IP level multipath protocol

Systems, methods, and devices of the various embodiments provide a multipath communication scheduler for an in-vehicle computing device, such as a vehicle's autonomous driving system, vehicle's telematics unit, vehicle's control system, etc. In various embodiments, a distributed leaky bucket based scheduler for an in-vehicle computing device may assign packets for transport to a plurality of modems based at least in part on the determined delivery delays. In various embodiments, delivery delays may be determined based on leaky bucket levels, burst sizes, delivery rates, and end to end delay estimates for each of the plurality of modems. In various embodiments, the scheduler may be one of a plurality of schedulers each associated with a separate stream of packets assigned to the plurality of modems and the leaky bucket levels may be determined on a per stream basis.

Distributed leaky bucket based multi-modem scheduler for multimedia streams

A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.

Horizontally-shared cache victims in multiple core processors

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.

Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency

A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.

Method and apparatus for global ordering to insure latency independent coherence

Systems and methods are disclosed herein to dynamically vary supply voltages and clock frequencies, also known as dynamic voltage scaling (DVS), in GPS receivers to minimize receiver power consumption while meeting performance requirements. For the baseband circuitry performing satellite acquisition and tracking, supply voltages and clock frequencies to the baseband circuitry are dynamically adjusted as a function of signal processing requirements and operating conditions for reducing baseband power consumption. Similarly, the supply voltage and clock frequency to the processor running navigation software and event processing are dynamically adjusted as a function of navigation performance requirements and event occurrences to reduce processor power consumption.

System and method for dynamic voltage scaling in a GPS receiver

An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetched instructions in the buffer have already been dispatched for execution. An input for each thread indicates that one or more of the already-dispatched instructions in the buffer has been flushed from execution. Control logic for each thread updates the indicator to indicate the flushed instructions are no longer already-dispatched, in response to the input. This enables the processor to re-dispatch the flushed instructions from the buffer to avoid re-fetching the flushed instructions. In one embodiment, there are fewer buffers than threads, and they are dynamically allocatable by the threads. In one embodiment, a single integrated buffer is shared by all the threads.

Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions

A processor prevents writeback race condition errors by maintaining responsibility for data until the writeback request is confirmed by an intervention message from a cache coherency manager. If a request for the same data arrives before the intervention message, the processor core unit provides the requested data and cancels the pending writeback request. The cache coherency data associated with cache lines indicates whether a request for data has been received prior to the intervention message associated with the writeback request. The cache coherency data of a cache line has a value of 'modified' when the writeback request is initiated. When the intervention message associated with the writeback request is received, the cache lines's cache coherency data is examined. A change in the cache coherency data from the value of 'modified' indicates that the request for data has been received prior to the intervention and the writeback request should be cancelled.

Preventing writeback race in multiple core processors

A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each thread and decreases it each time the execution pipeline executes an instruction of the thread. The scheduler includes an instruction execution rate for each thread. The scheduler increases the virtual water level based on the requested rate per a predetermined number of clock cycles. The scheduler includes virtual water pressure parameters that define a set of virtual water pressure ranges over the height of the virtual water bucket. When a thread's virtual water level moves from one virtual water pressure range to the next higher range, the scheduler increases the instruction issue priority for the thread; conversely, when the level moves down, the scheduler decreases the instruction issue priority for the thread.

Leaky-bucket thread scheduler in a multithreading microprocessor

Livelocks are prevented in multiple core processors by verifying that a data access request is still valid before sending messages to processor cores that may cause other data access requests to fail. A cache coherency manager receives data access requests from multiple processor cores. Upon receiving a data access request that may cause a livelock, the cache coherency manager first sends an intervention message back to the requesting processor core to confirm that this data access request will succeed. If the requesting processor core determines that the data access request is still valid, it directs the cache coherency manager to proceed with the data access request. The cache coherency manager may then send intervention messages to other processor cores to complete the data access request. If the requesting processor core determines that the data access request is invalid, it directs the cache coherency manager to abandon the data access request.

Avoiding livelock using a cache manager in multiple core processors

A multithreaded microprocessor includes a thread scheduler and voltage-frequency scheduler (VFS). The thread scheduler uses application-specified QoS requirements, which include required instruction completion rates, and instruction completion information from execution units to schedule the priorities of the threads at which the thread scheduler issues instructions to the execution units. Concurrently, the VFS uses the instruction completion and QoS information to calculate an aggregate utilization of the microprocessor by all the active threads when it is time to scale the voltage-frequency. The aggregate utilization is an effective measure of the amount of work left to be performed relative to the rate requirements. The VFS scales the voltage-frequency based on the aggregate utilization.

Multithreaded dynamic voltage-frequency scaling microprocessor

An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority generator that generates a priority for each instruction based on the register usage information and state information of instructions currently executing in an execution pipeline, and selection logic that dispatches at least one instruction from at least one thread based on the priority of the instructions. The priority indicates the likelihood the instruction will execute in the execution pipeline without stalling. For example, an instruction may have a high priority if it has little or no register dependencies or its data is known to be available; or may have a low priority if it has strong register dependencies or is an uncacheable or synchronized storage space load instruction.

Growing community of inventors

Sunnyvale, CA, United States of America

Sanjay Vishin