Quality Semiconductor Inc.

Sanjay V Gala

Ketan K Mehta

Varadarajan Srinivasan

Sandeep Khanna

Varad Srinivasan

Ruchir P Shah

A priority encoder for generating a priority-encoded address which identifies the highest priority request line. According to one priority scheme, the active request line having the lowest address has the highest priority. The priority encoder is capable of generating the priority-encoded address by determining information corresponding to the most significant bits of the priority-encoded address and using this information in the computation of less significant bits of the priority-encoded address. Using purely combinatorial logic, including switch elements, the priority encoder is capable of computing lower order bits using feedback signals resulting from the computation of higher order bits, allowing successive computation of priority-encoded address bits, without necessitating the use of clocks or delay elements.

Priority encoder for a content addressable memory system

A circuit and a method for detecting the presence of multiple active match lines in a content addressable memory is disclosed. The circuit includes at least one bus group for expressing a unary-encoded address portion of an active match line and, for each match line, an encoding circuit capable of activating a single member of each bus group according to the address of that match line when that match line is active. The multiple match detection circuit advantageously uses the property that each match line has a unique address, and therefore if there is more than one active match line, at least one bus group will have at least two active members. The multiple match detection circuit further comprises, for each bus group, an bus group detection-OR circuit for computing the logical bus group detection-OR of the members of that bus group. The multiple match detection circuit further comprises an OR circuit for computing the logical OR of the outputs of the bus group detection-OR circuits, for providing a multiple match flag which is active when two or more match lines are active and which is inactive otherwise.

Content addressable memory multiple match detection circuit

A semiconductor memory device is disclosed which is partitionable into random access memory (RAM) and content addressable memory (CAM) subfields, and with which incremental comparisons may be efficiently conducted. The apparatus generally includes a memory array of N data storage locations of M bits each which may be divided into predefined segments, a means for comparing a search word with all data words stored in the array, a means for generating a match signal when the bits of the search word match the bits of the data words, and a configuration register and a plurality of transfer gates for selecting which of the predefined array segments are to function solely as random access memory. The apparatus may additionally include a plurality of storage means, each corresponding to a segment of the memory array, for storing the match signals generated from that corresponding segment during a comparison.

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Sunnyvale, CA, United States of America

Sanjay V Gala