Micron Technology Incorporated

Sanjay Tiwari

Kyle B Wheeler

Jason T Zawodny

Richard Cameron Murphy

Todd A Marquart

Adam J Hieb

Adam C Guy

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Vector population count determination via comparison iterations in memory

A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

Memory sub-system event log management

Vector population count determination via comparsion iterations in memory

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

Smallest or largest value element determination

Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.

Span mask generation

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Comparison operations in memory

A length of a longest element can be determined in a memory device. An example method includes determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. The determination of the length of the longest element can include performing a number of AND operations, shift operations, and invert operations.

Longest element length determination in memory

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

Apparatuses and methods for performing corner turn operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

Growing community of inventors

Meridian, ID, United States of America

Sanjay Tiwari