Intel Corporation

Sanjay Sengupta

Sandip Kundu

Rajesh Galivanche

Sitaram Yadavalli

Dhiraj Goswami

A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine whether the device is free of structural defects.

Dft technique for avoiding contention/conflict in logic built-in self-test

A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Generalized fault model for defects and circuit marginalities

A test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain). The test system further includes a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable random data patterns (state elements joined together in the scan chain such that one state element is connected to a ground and the other state element is connected to a power supply) with desirable bit sequences to eliminate bus contention problems in the generated random data patterns. The test system further includes the integrated circuit device to be tested. The integrated circuit device receives the constrained random data patterns from the constraint checker and corrector module and outputs a test result. The test system further includes an X-masking module coupled to the integrated circuit device. The X-masking module receives the test result from the integrated circuit device, and it masks the test result by replacing unpredictable bit values (these are bit values generated due to not scanning some state elements in the scan chain) in the test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compress the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine the functionality of the integrated circuit device.

Constrained signature-based test

A technique for a scan design employing a register transfer level scan selection which requires that either all bits of a register are designated to have all scan or all non-scan properties. No separate elements (bits) of a register are selected for individual scan. By designating scan selection at the register level, register-transfer-level (RTL) specifications of a digital circuit can employ signal flow vectors at the register level and not at the conventional logic gate level. In one technique, a number of registers are grouped to have the same scan or non-scan property. Such grouping is used to provide a common template for inserting scan into multiple instantiated modules. The group designation for selecting scan or non-scan registers is also used to scan registers at the memory input, output, both input and output, or neither, which then can be used for testing memory devices.

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San Jose, CA, United States of America

Sanjay Sengupta