Cypress Semiconductor Corporation

Sanjay Rekhi

Nagendra Srinivas Cherukupalli

Somnath Paul

Paul D Keswick

Michael La Bouff

In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

Protection of integrated circuit gates during metallization processes

Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers. The scheduling policy may also include selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus, and not covered in the first priority selection, as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus, and not covered in the first and second priority selections, as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.

Scheduling store-forwarding of back-to-back multi-channel packet fragments

Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access

In one embodiment, a level in a process technology for an integrated circuit that has dummy metal patterns is represented as a level in a process model. The level of the process model may comprise a high-k dielectric to represent the dummy metal patterns. In the level of the process model, each metal line may be surrounded by a normal dielectric. If the process technology has voids or pockets of air in between the metal lines, then each void or air pocket may be placed in a normal dielectric in the process model. Among other advantages, this allows the process model to take into account the effects of the dummy metal patterns.

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Fremont, CA, United States of America

Sanjay Rekhi