Cirrus Logic Inc.

Magnum Semiconductor, Inc.

Mentor Graphics Corporation

Western Digital Technologies, Inc.

Siemens Industry Software Gmbh

Austemper Design Systems Inc.

Sanjay Ramakrishna Pillay

Brian F Bounds

William Lynn Gallagher

Srikanth Rengarajan

Arun Kumar Gogineni

Wei T Huang

Sanjay Subbarao

Raghunath Krishna Rao

Hasibur Rahman

Michael Allan Kost

Nariankadu Datatreya Hemkumar

Khoi Mai

Girish Subramaniam

Richard Dean Putman

Ronald D Wiese

Arum Kumar Gogineni

Luo Zheng

Dimitri Pantelakis

Peng Liu

This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.

Parallel fault simulator with back propagation enhancement

This application discloses a computing system implementing a functional safety validation tool to locate a vulnerable section of an electronic system described in a circuit design, select safety circuitry configured to monitor the vulnerable section of the electronic system, and modify the circuit design by inserting the safety circuitry and control circuitry into the circuit design. The control circuitry and the safety circuitry can detect faults in the vulnerable section of the electronic system. The functional safety validation tool can generate a logical equivalency check script for the modified circuit design, wherein a logical equivalency checking tool can be utilized to determine whether the modified circuit design is logically equivalent to the circuit design. The functional safety validation tool can generate a test bench for the modified circuit design, wherein at least one verification tool can be utilized in a verification environment to simulate the modified circuit design.

Functional safety synthesis

A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Fault campaign in mixed signal environment

A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device

Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use.

Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation

Systems and methods for analyzing and reducing the failure rates due to soft errors in a design are provided. One such method involves analyzing the design by reading the design from a register-transfer-level language description or a netlist, manufacturing process soft error information, library information and timing constraints for the design to generate the failure in time (FIT) rate for the modules in the design. Another such method involves using the design and a list of memories that need error correction code inserted automatically and limiting the impact to the clock cycle, by analyzing the timing to the inputs and from the outputs of the memories and inserting an in-line or a late timing wrapper, which includes the ECC insert during writes, and ECC check and correct during reads, identifying the registers that need to be shadowed and used in the delayed ECC correct cycle, identifying the clock gating required for various elements in the design to get the correct logic at the conclusion of the re-play cycle of ECC correction in case of late timing ECC correction.

Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof

Systems and methods for predicting the compressibility of data in a flash storage device are provided. One such method involves extracting byte intervals from the block of data, each of the byte intervals consisting of a preselected number of bytes, performing a hash function to map the byte intervals into a plurality of bins, the plurality of bins comprising one bin for each possible value of the byte intervals, incrementing a hit count each time more than one of the byte intervals is mapped into a single bin of the plurality of bins, and determining whether to compress the block of data based on a comparison of a ratio of the hit count to a total number of the byte intervals and a preselected threshold. This method may be implemented in hardware to ensure fast and efficient execution.

Systems and methods for predicting compressibility of data

A scan including data and shift inputs, and input selection circuitry for selecting between the data and shift inputs during normal, capture, and shift modes in response to only a first control signal and a second control signal. The input selection circuitry includes a first storage element for storing a bit representing a state of the first control signal in response to a change in state of the second control signals and multiplexing circuitry. The multiplexing circuitry is operable in the normal mode to select the data input in response to a first state of the second control signal, in the capture mode to select the data input when the bit stored in the first storage element represents a first state of the first control signal, and in the shift mode to select the shift input when the bit stored in the first storage element represents a second state of the first control signal. A second storage element stores, in response to the first state of the first control signal, data presented at the selected one of the data and shift inputs.

Scan cells with minimized shoot-through and scan chains and integrated circuits using the same

A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular start address, where the start address is specified in conjunction with the specific program instruction. An end address is also specified in conjunction with the specific program instruction and the processor re-directs control upon completion of code execution between the start and end address to either another specified address, or to a stored program counter value corresponding to the next instruction in sequence after the specific program instruction. A loop count may also be supplied for repeatedly executing the code between the start and end address until the count has expired.

Processor and processing method for reusing arbitrary sections of program code

A method of deinterlacing includes generating a deinterlaced display frame including a reference field of lines of display pixels of a first parity and a generated field of lines of display pixels of a second parity. A frame motion map is generated which includes bits representing a presence of motion or an absence of motion at the display pixels of the reference and generated fields. Testing is performed for the presence of motion or the absence of motion at a selected display pixel of the reference field utilizing the frame motion map. In response to detecting a presence of motion at the selected display pixel of the referenced field, replacing a pixel value corresponding to the selected display pixel with a pixel value generated by interpolating between display pixel values corresponding to neighboring display pixels in the generated field.

Systems and methods for reducing noise during video deinterlacing

A method of adaptive deinterlacing of video data includes generating a selected pixel value at a given pixel position of a current interlaced field by either weaving a pixel value from another interlaced field, when no motion is detected at the pixel position, or by interpolating between other selected pixel values of the current field, when motion is detected at the pixel position. When the pixel value is generated by weaving, a test for feathering is performed. If feathering is detected, a further check is performed for motion at the pixel position over a selected number of preceding fields. In the absence of motion over the preceding fields, the weaved pixel value is utilized as the selected pixel value. If motion is detected over the preceding fields, interpolation is performed between selected pixel values of the current field to generate the selected pixel value.

Circuits and methods for deinterlacing video display data and systems using the same

A method of detecting a stream of video data generated utilizing a pull-down technique includes receiving a sequence of fields of interlaced video data. For each pair of a plurality of pairs of the fields of interlaced video in the sequence, pixel values corresponding to pixel positions of pixel lines of a first parity of a first field of the pair of fields are weaved with pixel values corresponding to pixel positions of pixel lines of a second parity of a second field of the pair of fields. For each pixel value corresponding to each pixel position of each pixel line of the second field of the pair of fields after weaving, a check is made for feathering at the corresponding pixel position due to motion. The pixel positions with feathering due to motion in the second field of the pair of fields are counted, and, for the plurality of pairs of fields in the sequence, a check is made for a pattern in the number of counted pixel positions with feathering due to motion in the second field of each pair of fields to determine if the video data comprises data generated utilizing a pull-down technique.

Circuits and methods for detecting 2:2 encoded video and systems utilizing the same

A method of detecting a change in a sequence of video data fields generated from a progressive scan source includes receiving first and second interlaced fields of a corresponding progressive scan frame from a sequence of interlaced fields generated from progressive scan source. Pixel values corresponding to pixel positions of pixel lines of a first parity of the first field are weaved with pixel values corresponding to pixel positions of pixel lines of a second parity of the second field. For each pixel value corresponding to each pixel position of each pixel line of the second field after weaving, a check is performed for the corresponding pixel position for feathering due to motion. A number of detected pixel positions with feathering due to motion is counted and compared against a threshold. A determination is made that the sequence of fields generated from the progressive scan source has not changed when the number of counted pixel positions due to motion is below the threshold and a determining that the sequence of fields generated from the progressive scan source has changed when the number of counted pixel positions due to motion is above the threshold.

Systems and methods for detecting a change in a sequence of interlaced data fields generated from a progressive scan source

A method interpolating pixel values includes calculating a difference value between pixel values corresponding to a first display pixel on a first display line and a second display pixel on a second display line, the first and second display pixels defining a possible edge angle of an object on a display. Another difference value is calculated between pixel values corresponding to a third display pixel of the first display line and a fourth display pixel of the second display line, the third and fourth display pixels defining a second angle on the display. A determination is made as to whether the difference value is less than or equal to the another difference value, and when the difference value is less than the another difference value, interpolation is performed between a pixel value corresponding to a selected display pixel on the first display line and another pixel value corresponding to a selected display pixel on the second display line to generate a pixel value corresponding to a display pixel on a third display line.

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Sanjay Ramakrishna Pillay