Intel Corporation

Sanjay R Ravi

Adee Ofir Ran

David G Ellis

Amir Mezer

Stephen J Peters

Jeffrey M Shuey

Ophir Gazinski

A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.

Method, apparatus, and system for measurement of noise statistics and bit error ratio estimation

In one embodiment, a receiver is coupled to a transmitter via an interconnect. The receiver includes a voltage margining circuit to receive non-deterministic data transmitted by the transmitter via a multi-level signaling scheme and to generate a bit error report including bit error information obtained at a plurality of margining levels. Other embodiments are described and claimed.

Method, apparatus and system for performing voltage margining

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Hillsboro, OR, United States of America

Sanjay R Ravi