National Semiconductor Corporation

Sanjay Popli

Scott K Pickett

David Warren Hawley

Frederick Furtek

Rafael C Camarota

Jim Sutherland

Shankar Moni

Venkata Alturi

Benjamin S Ting

Tim Garverick

Shao-Pin Chen

Arthur Smith, Jr

Shin-Mann Day

The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins. The array further includes a configuration circuit for generating external addresses and that can be controlled through a data configuration file fetched from an external storage medium.

Configuration features in a configurable logic array

The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a dynamic tristate bus driver associated with each logic cell and connectable to the local busses associated with the corresponding logic cell and means for controlling the dynamic tri-state driver through one or more combinations of inputs to the logic cell.

Flexible high impedance control in a cole cell in a configurable logic

A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.

Versatile and efficient cell-to-local bus interface in a configurable

The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. Adjacent abutting cells logic cells are interconnectable via horizontal and vertical configurable interconnections running between adjacent cells. Furthermore, configurable diagonal interconnections run between diagonally adjacent abutting logic cells in the array.

Diagonal wiring between abutting logic cells in a configurable logic

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Sunnyvale, CA, United States of America

Sanjay Popli