Advanced Micro Devices Corporation

University of Michigan

Sanjay Pant

Srilatha Manne

Youngtaek Kim

David Theodore Blaauw

Michael J Schulte

Rajagopalan Desikan

A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Power control for multi-core data processor

A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

Guardband reduction for multi-core data processor

An integrated circuit () is provided with power regulating circuitry () serving to actively regulate the voltage difference between a first power supply rail Vand a second power rail Vbeing used to supply electrical power to processing circuitry (). A voltage regulating capacitor Chas one terminal connected to the first power rail Vand a second terminal selectively connected to either the second power rail Vor a third power rail V. Should a voltage undershoot be detected by voltage sensing circuitry, then the capacitor Cis connected to the third power rail Vso as to dump at least part of charge C, Vin capacitor Conto the first power rail Vand resist the voltage drop. During normal operation, charge is accumulated into the capacitor C. An additional load device Tis provided to lower the voltage difference should an overshoot be detected.

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Fort Collins, CO, United States of America

Sanjay Pant