Apple Inc.

Sanjay Pant

Fabio Gozzini

Shawn Searles

Jay B Fletcher

Hubert Attah

Wenxun Huang

Jared L Zerbe

Brian S Leibowitz

Jonathan F Bolus

Hao Zhou

Inder M Sodhi

Vincenzo Bisogno

Ludmil N Nikolov

Nathan F Hanagami

Floyd L Dankert

Enrico Zanetti

Tiago Filipe Galhoz Patrao

Wei Yu Chen

Jafar Savoj

Alberto Alessandro Angelo Puggelli

Talbott Mead Houk

Joseph T DiBene, Ii

Mark A Yoshimoto

Siarhei Meliukh

Nikola Jovanovic

Di Zhao

Alessandro Molari

Hartmut Sturm

Sarfraz Shaikh

Seyedeh Maryam Mortazavi Zanjani

Sotirios Zogopoulos

Tristan R Hudson

Ofir Gilad

John J Sullivan

Nicola Florio

Chad L Olson

Koushik Vaithyanathan

Alberto Puggelli

Jonathan A Dutra

Georg Diebel

A power converter with slew rate detection is disclosed. A power converter comprises a plurality of phase circuits coupled to a regulated power supply line via corresponding ones of a plurality of inductors. A first control loop generates, using digital samples and based on comparisons of a reference voltage to a voltage on the regulated power supply line, a first plurality of control signals. A second control loop, using the digital samples, generates a second plurality of control signals based on a rate of change of the voltage of the regulated power supply line. The second control loop causes the first control loop to control the plurality of phase circuits in response to detecting that the rate of change is within a specified range, and causes the second control loop to control the plurality of phase circuits, in response to detecting that the rate of change exceeds the specified range.

Slew rate detection in power converter with digital current mode control

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

A power delivery system included in a computer system uses multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. An embodiment of the power delivery system includes an input power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.

Scalable power delivery system

A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.

Current measurement for power converter circuits

A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.

Regulator switch array

A power delivery system included in a computer system using multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. The power delivery system includes a step-down power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.

A voltage regulator circuit included in a computer system may include multiple phase circuits coupled to a regulated power supply line via corresponding one of multiple inductors. The phase circuits may modify a voltage level of the regulated power supply line using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

Digital current mode control for multi-phase voltage regulator circuits

Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).

Detecting power supply noise events and initiating corrective action

A power management circuit included in a computer system regulates a voltage level of a power supply node used by other circuits in the computer system. The power management circuit includes a control circuit and multiple phase circuits coupled to the regulated power supply node via corresponding inductors. The control circuit selectively activates particular ones of the multiple phase circuits allowing them source respective currents to the regulated power supply node. The control circuit also selectively activates particular ones of other phase circuits that are external to the power management circuit and coupled to the regulated power supply node via their own corresponding inductors. Once activated, the external phase circuits source respective currents to the regulated power supply node via their corresponding inductors.

Multi-phase power converter with external phase circuits

A voltage regulator circuit included in a computer system may include multiple phase circuits each coupled to a regulated power supply node via a corresponding inductor. The phase circuits may modify a voltage level of the regulated power supply node using respective control signals generated by a digital control circuit that processes multiple data bits. An analog-to-digital converter circuit may compare the voltage level of the regulated power supply node to multiple reference voltage levels and sample the resultant comparisons to generate the multiple data bits.

A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor is configured to regulate a voltage level of a power supply node using a particular one of multiple available operating modes. In response to receiving a command to reduce the voltage level of the power supply node, the power converter circuit begins to reduce the voltage level of the power supply node, while autonomously selecting different ones of available operating modes. The power converter circuit may compare to the voltage level of the power supply node to boundary levels and select a different operating mode when the voltage level of the power supply node exceeds one of the boundaries. By switching operating modes during the negative slew of the voltage level of the power supply node, the power converter may maintain a target efficiency during the reduction in voltage.

Negative slew rate control for power converters

An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.

Non-volatile memory control circuit with parallel error detection and correction

Growing community of inventors

Santa Clara, CA, United States of America

Sanjay Pant