Ramtron International Corporation

Other

Hana Microelectronics, Inc.

Sanjay Mitra

Sirirat Silapapipat

Vanapong Kwangkaew

Stanley C Perino

George Argos, Jr

Preecha Bootwicha

Krisadayut Chansawang

Holli Harper

Vic Lau

Holden Hackbarth

A sensor comprising a light emitter and light detector coupled directly with or formed directly on a lead frame and directly covered and encapsulated by a layer of light transmissive compound. A gap in the light transmissive compound between the light emitter and the light detector wherein in some embodiments the gap can be filled with a light blocking barrier material.

Proximity sensor with light inhibiting barrier comprising a gap having a cross-section with parallel walls substantially perpendicular to the top surface of an optically transmissive material

A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light transmissive compound. A gap in the light transmissive compound between the light emitter and the light detector filled with a light blocking barrier.

Proximity sensor with light blocking barrier comprising a gap having a cross-section with parallel walls between emitter and detector

A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light transmissive compound. A gap in the light transmissive compound between the light emitter and the light detector filled with an infrared ink. In some embodiments, an infrared ink can cover at least a portion of a top surface of the sensor and define apertures above the light detector and/or light emitter.

Proximity sensor with infrared ink coating

A sensor comprising a light emitter and light detector directly covered and encapsulated by a layer of light blocking compound. The light blocking compound can be thick enough between the light emitter and light detector to block substantially all light emitted by the light emitter from reaching the light detector directly, but be thin enough above the light emitter and light detector to allow at least some level of light emitted by the light emitter to escape out of the sensor, be reflected by another object, re-enter the sensor, and survive passing through the light blocking compound to enter the light detector.

Proximity sensor with light blocking compound

A plastic package assembly method suitable for ferroelectric-based integrated circuits includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures. The plastic package assembly method uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving yields and reliability. The assembly method uses a snap cure die attach step, a die coat followed by a room temperature cure, and formation of the plastic package with room temperature curable molding compounds not requiring a post mold cure. Front and back marking of the plastic package is accomplished using either an infrared or ultraviolet curable ink followed by minimum cure time at elevated temperature, or by using laser marking.

Plastic package assembly method for a ferroelectric-based integrated circuit

A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H,O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion

A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

Yield enhancement technique for integrated circuit processing to reduce

A test method for ferroelectric memories includes the steps of: functionally testing the ferroelectric memories to determine functional yield; storing the ferroelectric memories for at least eight hours; writing an initial pattern into the ferroelectric memories; baking the ferroelectric memories; reading the initial pattern to determine same state yield; writing an inverse pattern into the ferroelectric memories; reading the inverse pattern to determine opposite state yield; and again writing the initial pattern into the ferroelectric memories. The steps of baking, reading the initial pattern and writing the inverse pattern, and reading the inverse pattern and writing the initial pattern are repeated for a number of test cycles. The ferroelectric memories are baked at a temperature of about 150.degree. C. for a predetermined duration that is incremented with each successive test cycle.

Same state and opposite state diagnostic test for ferroelectric memories

Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array. The electrical cycling operation restores the symmetry and location of the hysteresis loop. The ferroelectric capacitor is then returned to the virgin state by a depoling operation. The electrical depoling operation is achieved by writing each capacitor in the array to a logic one and a logic zero at the full five volt power supply level initially, and then repeating each write cycle at decreasing power supply levels. The writing cycles are continued until the power supply is reduced to a minimum functional level and the polarization on the capacitors has been substantially removed.

Growing community of inventors

Colorado Springs, CO, United States of America

Sanjay Mitra