Cypress Semiconductor Corporation

Sun Microsystems, Inc.

Netlogic Microsystems, Inc

Sanjay M Wanzakhade

David V James

Jagadeesan Rajamanickam

Michael C Stephens, Jr

Ajay Bhatia

Shashank Shastry

Richard K Chou

A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values.

Magnitude comparator circuit for content addressable memory with programmable priority selection

Dual match line circuits having race condition improvements. A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. A positive feedback circuit coupled to the miss match line may accelerate its discharge. The hit match line may be additionally coupled to discharge through a discharge path. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

Race condition improvements in dual match line architectures

A dual match line circuit may include precharge logic configured to precharge each of a hit match line, a miss match line and an evaluate node to an asserted state, where a coupling device couples the hit and miss match lines to the evaluate node. The miss match line may discharge through a number of load devices that may be activated by respective miss signals. The hit match line may be additionally coupled to discharge through a pair of devices connected in series, one of which may be activated by a hit signal, and the other of which may be activated by the miss match line. The hit and miss match lines may be electrically isolated from one another, such that when any of the respective miss signals is asserted, current from the hit match line does not discharge through the miss match line.

Dual match line architecture for content addressable memories and other data structures

A priority encoder circuit () for a content addressable memory (CAM) device is disclosed that may include a priority selection circuit () that receives match results (Mto Mz) and provides prioritized match results (Pto Pz), and a logic section () that logically combines prioritized match results (Pto Pz) to generate a smaller number of encoder inputs (RWLto RWLr). A logic section () can also generate a first portion (ID) of an encoded value (IDto IDX). Encoder entries (-to-) may each generate a second portion (IDto IDX) of an encoded value (IDto IDX).

Priority encoder circuit for content addressable memory (CAM) device

According to one embodiment, a search engine device () may include an input (), search portion (), and a vote portion (). A vote portion () may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion () may generate an output response having its own precedence information.

Search engine device and method for generating output search responses from multiple input search responses

A content addressable memory (CAM) device () may include a number of blocks (-[11]) that each generate CAM search results and result compare circuits (-[11] that receive CAM search results from multiple blocks (-[11]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (-[11]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (-[&#x2212;11]).

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San Jose, CA, United States of America

Sanjay M Wanzakhade