Synopsys, Inc.

Stmicroelectronics International N.v.

Hcl Technologies Limited

Sanjay Kumar Yadav

Prashant Dubey

Amit Khanuja

G Penaka Phani

Shailendra Sharad

Vaibhav Verma

Vijit Gadi

Praveen Kumar Verma

Rohan Makwana

Shallendra Sharad

Anubhav Agarwal

Gaurav Ahuja

Gaurav Vrati

Guarav Ahuja

Himanshu Tagra

Disclosed is a method and system for assessing the authenticity of a communication. The method comprises receiving data of the communication by the processor between one or more participants. Further, extracting one or more features by the processor from the data by using data extraction techniques. Further, comparing the one or more features by the processor with predefined threshold features stored in a feature repository. Further, generating, one or more authenticity attributes by using one or more trained Artificial Intelligence (AI) models applied over the one or more features, along with results of the comparing. Each of the one or more authenticity attributes generates a recommendation output, providing the authenticity of the communication.

System and method for assessing authenticity of a communication

A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate a read clock signal in response to a read request signal. The level shifter is adapted to supply a reference wordline read signal in response to the read clock signal. The comparator is adapted to select a delay between the read clock signal and the reference wordline read signal in response to a difference between the first and second supply voltages.

Self-adjustable self-timed dual-rail SRAM

Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.

Controlling timing of negative charge injection to generate reliable negative bitline voltage

An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.

Circuit for generating negative bitline voltage

A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Sense amplifier using reference signal through standard MOS and DRAM capacitor

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Greater Noida, India

Sanjay Kumar Yadav