Dell Products Inc.

Intel Corporation

The Boeing Company

Zebra Technologies Corporation

Virsec Systems, Inc.

Sanjay Kumar

Bhyrav M Mutnury

Abhishek R Appu

Joydeep Ray

Altug Koker

Elmoustapha Ould-Ahmed-Vall

Prasoonkumar Surti

Subramaniam M Maiyuran

Vasanth Ranganathan

Varghese George

Om Prakash

Lakshminarayanan Striramassarma

Pattabhiraman K

Niranjan L Cooray

Valentin Andrei

Sungye Kim

Pratik M Marolia

William B Sadler

Mallikarjun Vasa

Vijendera Kumar

Guadalupe J Garcia

Shantanu Bhattacharya

Pulak Bhushan

Arun Reddy Chada

Megha Sahu

Vijender Kumar

Kranthi Kumar Gadde

Vikram B Mangeshwar

Malikarjun Vasa

Sunil Pathania

Mallikarjun Goud Vasa

Manoj Paul

Rao Gattupalli

Jaya Gowri Anand Burji

Arun Vignesh Palanichamy

Naga Hara Sathya Sree Tammisetti

Sukumar Muthusamy

Sathvika Bandi

Ashish Shrivastava

Seema P K

A printed circuit board substrate including multiple sets of glass rows. The multiple sets of glass rows include a first set of glass rows, a second set of glass rows, and a third set of glass rows. The first set of glass rows extend in a first direction. The second set of glass rows extend in a second direction that is perpendicular to the first direction. The third set of glass rows extend in a third direction that is parallel to the first direction. The resin holds the multiple sets of glass rows together and to fill pockets between the multiple of sets of glass rows.

Fiber weave in a printed circuit board substrate

An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Integrated thermal-electrical co-simulation

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

A method in a computing device includes: capturing, via a sensor, an image of an indicium; determining a confidence level associated with machine recognition of the indicium; based on the confidence level, selecting a feedback attribute; prior to outputting content encoded in the indicium, generating, via an output device, a feedback signal having the feedback attribute, wherein the attribute is configured to indicate a likelihood of success of a decode event to decode the content encoded in the indicium.

Machine recognition confidence-based visual feedback devices and methods

Embodiments determine event, e.g., performance degradation, security breach, etc., occurrence based on telemetry data. An embodiment receives telemetry data, e.g., data based on an HTTP transaction, and a rule associated with the telemetry data. The rule defines one or more filters for processing the telemetry data. In turn, a rule engine is modified in accordance with the received rule. The received telemetry data is processed with the modified rule engine to determine event occurrence.

System and method for telemetry data based event occurrence analysis with rule engine

An add-in card printed circuit board (PCB) includes a body portion and a card edge portion. The body portion includes a circuit trace associated with a high-speed data communication interface. The card edge portion includes contact fingers, and is configured to be inserted into a card edge connector of an information handling system. The contact fingers include a signal contact finger coupled to the circuit trace, and a ground contact finger that is located adjacent to the signal contact finger. The ground contact finger includes a ground via that couples the ground contact finger to a ground plane layer of the add-in card PCB. The ground via is located half way within the body portion and half way within the card edge portion.

Add-in card connector edge finger optimization for high-speed signaling

A sound attenuation panel that includes an incident wall and a frame unit connected to the incident wall. The incident wall defines an aperture therethrough. The frame unit includes multiple spoke members spaced apart from one another and radially extending from one or more central hub openings of the frame unit. The one or more central hub openings align with the aperture of the incident wall. The frame unit defines channels between adjacent pairs of the spoke members. The channels fluidly connect to the one or more central hub openings. The frame unit is configured to receive sound waves into the central hub opening through the aperture of the incident wall to dissipate the sound waves through the channels between the spoke members.

Sound attenuation panel and methods of constructing and installing the same

A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Printed circuit board having vias arranged for high speed serial differential pair data links

A printed circuit board (PCB) for an information handling system includes first and second signal vias, and a quantity of ground vias. The first signal via is separated from the second signal via by a first distance. The ground vias are grouped into pairs and each ground via of each pair is separated from one of the first or second signal vias by a second distance. The location of the ground vias in terms of an angle between the ground vias is given as an expression relating the first distance, the second distance, and the quantity of ground vias.

System and method for ground via optimization for high speed serial interfaces

A composite panel assembly includes first and second elastic membranes and a structure. The structure has a first side mounted to the first elastic membrane and a second side mounted to the second elastic membrane. The structure includes a first honeycomb layer, a second honeycomb layer, and a plurality of necks. The first honeycomb layer has partition walls defining resonance cavities that are covered by the first elastic membrane along the first side. The second honeycomb layer has partition walls defining resonance cavities that are covered by the second elastic membrane along the second side. The necks are disposed between and connect the first and second honeycomb layers. Each neck defines a channel that is fluidly connected to a corresponding one of the resonance cavities of the first honeycomb layer and a corresponding one of the resonance cavities of the second honeycomb layer.

Composite sound absorption panel assembly

Methods and mechanisms for mitigating attenuation in a printed circuit board connection may include selecting the relative permittivities of resin layers proximate to the connection to control connection frequency resonances such that the attenuation of signals in the connection due to frequency resonance is mitigated.

Method for mitigating signal attenuation in printed circuit board connections

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Bengaluru, India

Sanjay Kumar