Texas Instruments Corporation

Sanjay Krishna Hulical Vijayaraghavachar

Wilson Pradeep

Srivaths Ravi

Rajesh Kumar Tiwari

Raashid Moin Shaikh

Khushboo Agarwal

Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

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Karnataka, India

Sanjay Krishna Hulical Vijayaraghavachar