Cypress Semiconductor Corporation

Sanjay K Sancheti

George M Ansel

Suwei Chen

Jeffery Scott Hunt

Anup Nayak

William G Baker

James E Kelly

Gary Austin Gibbs

Shiva P Gowni

Gareth Feighery

Shailja Garg

Bo Gao

Sudhir S Moharir

Lingsong Xu

Disclosed are a circuit and a method for controlling dynamic in-rush current in a power management circuit. The circuit includes a current limiting unit having a first quantity of sleep mode devices. A voltage drop minimization unit is coupled to the current limiting unit and has a second quantity of sleep mode devices. The second quantity of sleep mode devices is greater than the first quantity of sleep mode devices. A sequential enabling unit is coupled to both the current limiting unit and the voltage drop minimization unit. The sequential enabling unit is configured to turn on the voltage drop minimization unit after the current limiting unit in accordance with a predetermined delay.

Circuit and method for dynamic in-rush current control in a power management circuit

A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.

Configurable power controller

An arbiter circuit () can include a latch circuit () that latches competing input signals (MATCHand MATCH) to generate signals on latch output (-and-). A filter section () can prevent metastable states of latch output signals from propagating through to output signals (BUSYand BUSY). In addition, filter section () can generate output signals (BUSYand BUSY) having one set of values when both inputs are inactive, and a second set of values when latch () is in the metastable state.

Arbiter circuit and signal arbitration method

In one embodiment of the present invention, a phase generator, comprising a plurality of delay blocks, is coupled in a feedback loop with a phase detector. When in an open loop mode, the phase generator is operable as a voltage controlled delay line. The phase detector compares an input signal with a first output signal of the phase generator and generates a first control signal based thereon. The phase generator is also coupled in a feedback loop with a phase-frequency detector. When in a closed loop mode, the phase generator is operable as a voltage controlled oscillator and the phase-frequency detector compares the input signal with a second output signal of the phase generator. The phase-frequency detector then generates a second control signal based thereon.

Wide frequency range DLL with dynamically determined VCDL/VCO operational states

A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit. Also, the circuit, system, and method support double data rate (DDR) data and echo clock generation, where the echo clock transitions in sync with the DDR output.

System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output

A data path () can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path () can be compact circuit structure, needing only an additional mode multiplexer () and inverter over a conventional D-type master-slave flip-flop.

Data path configurable for multiple clocking arrangements

A multi-port memory cell () can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell () can be cleared by shorting complementary data nodes (-and-) together. Write data can then be placed on a bit line. Complementary data nodes (-and-) can then be isolated once again, resulting in the write data being latched within the memory cell (). An access method () for a multi-port memory cell is also described.

Multi-port memory cell and access method

A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.

Delay circuit that scales with clock cycle time

A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.

Method and system for high resolution delay lock loop

A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second value in response to a data input transition, (B) holding in a ready state until the data input is stable and (C) writing stable data into a memory array.

Method and circuitry for writing data

An apparatus comprising a first circuit, a reset circuit and an output circuit. The first circuit may be configured to generate one or more state signals in response to (i) a first and a second write control signals and (ii) one or more control signals. The reset circuit may be configured to generate the one or more control signals in response to (i) a global write signal and (ii) the first and second state signals. The output circuit may be configured to generate a third and fourth write control signal in response to (i) the global write signal (ii) a data input signal and (iii) the first and second state signals. In one example, the third and fourth write control signals may generate a pulse on either the third or the fourth write control signals in response to a transition of the data input signal.

A circuit and method comprising (a) a first circuit configured to generate an output signal having a variable pulse width in response to an (i) input signal and (ii) a control signal and (b) a second circuit configured to generate the control signal in response to (i) the input signal and (ii) a test input. In one example, the first circuit may comprise a register configured to present the output signal and an edge detection circuit configured to present a second control signal to said second circuit. In another example, the second circuit may comprise a plurality of first gates that may generate the output signal in further response to the second control signal.

Self-timed synchronous pulse generator with test mode

A write control circuit for a semiconductor memory device includes a conventional write path responsive to a control input (e.g., an external write enable signal) to control the beginning of a write operation for a write driver, whilst a separate dedicated write disable path, responsive to the same control input, controls the end of the write operation for the write driver. The invention separates the end of write from the beginning of write by introducing a fast dedicated path designed primarily for ending the write. This dedicated path contains dedicated logic to generate an end of write signal at the disabling edge of the control input to disable the write driver quickly before a new memory cell is selected.

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Starkville, MS, United States of America

Sanjay K Sancheti