University of Texas System

Micron Technology Incorporated

Texas Instruments Corporation

Other

Advanced Micro Devices Corporation

The Texas A&m University System

Darpa

Sanjay K Banerjee

Shubneesh Batra

Monte Manning

John Damiano, Jr

Leonard Franklin Register, Ii

Emanuel Tutuc

Allan MacDonald

LeTien Jung

Sidlgata V Sreenivasan

Michael Robert Watts

Dharmendar Reddy Palle

Akhila Mallavarapu

Jaydeep Kulkarni

David L Kencke

Luigi Colombo

Satwinder S Malhi

Hisashi Shichijo

Shyam G Garg

William Thomas Lynch

Chung-You Hu

Robert B Richart

Chuanbin Mao

Richard H Womack

Ben G Streetman

Hua Chen

Aloysious F Tasch, Jr

Al F Tasch, Jr

Shan Tang

Rik Dey

Bhagawan R Sahu

Priyamvada Jadaun

Suryanarayana Bhattacharya

Jiwon Chang

Seyoung Kim

Inti Sodemann

Xiangdong Chen

Xuehao Mou

Qiqing Ouyang

Bahniman Ghosh

A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Catalyst influenced chemical etching for fabricating three-dimensional SRAM architectures

A magnetic solid state device is disclosed. The magnetic solid state device includes a substrate and a topological insulator deposited on top of the substrate. The magnetic solid state device also includes a first perpendicular magnetic anisotropy (PMA) bit having a reference PMA layer located on the topological insulator, and a second PMA bit having a free PMA layer located on the topological insulator. A gate contact is utilized to receive various predetermined voltages for controlling the Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions between the reference PMA layer in the first PMA bit and the free PMA layer in the second PMA bit.

Method for fabricating magnetic solid state devices

A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits. Furthermore, the easy-in-plane magnetic films may be subdivided into regions coupled through exchange interactions and the in-plane fixed magnetic layers in the input magnetic stacks can be used in non-volatile logic and memory.

Transistor that employs collective magnetic effects thereby providing improved energy efficiency

A method for fabricating a flash memory device where the flash memory device includes a substantially uniform size and spatial distribution of nanoparticles on a tunnel oxide layer to form a floating gate. The flash memory device may be fabricated by defining active areas in a substrate and forming an oxide layer on the substrate. A self-assembled protein lattice may be formed on top of the oxide layer where the self-assembled protein lattice includes a plurality of molecular chaperones. The cavities of the chaperones may provide confined spaces where nanocrystals can be trapped thereby forming an ordered nanocrystal lattice. A substantially uniform distribution of nanocrystals may be formed on the oxide layer upon removal of the self-assembled protein lattice such as through high temperature annealing.

Nanoparticles in a flash memory using chaperonin proteins

A Topological INsulator-based field-effect transistor (TINFET) is disclosed. The TINFET includes a first and second gate dielectric layers separated by a topological insulator (TI) layer. A first gate contact is connected to the first gate dielectric layer on the surface that is opposite the TI layer. A second gate contact may be connected to the second gate dielectric layer on the surface that is opposite the TI layer. A first TI surface contact is connected to one surface of the TI layer, and a second TI surface contact is connected to the second surface of the TI layer.

Topological insulator-based field-effect transistor

A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.

Bi-layer pseudo-spin field-effect transistor

A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene

A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.

Incorporating gate control over a resonant tunneling structure in CMOS to reduce off-state current leakage, supply voltage and power consumption

A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure extending from the source region and substrate. The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si Ge extending to and abutting the drain region. The mole fraction of Ge can increase towards the drain region either uniformly or in steps. In one embodiment, the doping profile of the channel region is non-uniform with higher doping near the source region and lower doping near the drain region.

Submicron MOSFET having asymmetric channel profile

A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Thin film transistors and method of forming thin film transistors

A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium. A method of increasing the size of individual crystal grains in a polycrystalline silicon alloy includes, a) providing germanium atoms within a layer of polycrystalline silicon to form a polycrystalline silicon-germanium alloy; and b) heating the polycrystalline silicon-germanium alloy to an effective temperature for an effective period of time to cause individual polycrystalline silicon grains within the alloy to increase their size from prior to the heating step.

Bottom-gated thin film transistors comprising germanium in a channel region

A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.

High mobility heterojunction transistor and method

A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.

Floating gate transistor having buried strained silicon germanium channel layer

Growing community of inventors

Austin, TX, United States of America

Sanjay K Banerjee