Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Sanjay Jinturkar

Paul Gerard D'Arcy

C John Glossner

Dean Batten

Kent E Wires

Jesse Thilo

Stamatis Vassiliadis

David Whalley

Ramesh V Peri

Lincoln A Fajardo

Jay Patrick Wilshire

Pamela C Deschler

Gang-Ryung Uh

Vincent Phuoc Cao

Kamesh Peri

Yuhong Wang

The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. The predicate dependencies can be handled using, e.g., a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler. One or more instructions are then grouped in a code block which includes a field indicating the dependencies associated with those instructions, and the instructions are then, e.g., either stalled or decoded serially, based on the dependencies present in the code block. By eliminating unnecessary processing for false-predicate instructions, the invention significantly reduces the power consumption of the processor.

Method and apparatus for reducing power consumption in a pipelined processor

A method for simulating a first processor (e.g., target processor) on a second processor (e.g., host processor) includes translating assembly language instructions associated with the first processor into 'C' language code. The 'C' language code is then compiled by a compiler program running on the second processor. The compiled code is then executed by the second processor to simulate the first processor. For example, the code may be checked to determine whether it is functionally correct and/or run-time statistics may be collected regarding the program associated with the first processor.

Methods and apparatus for simulating external linkage points and control transfers in source translation systems

The invention provides compiler loop optimization techniques to take advantage of a zero overhead loop mechanism (ZOLM) in a processor, e.g., a ZOLM in the form of a zero overhead loop buffer (ZOLB). In an illustrative embodiment, a compiler generates a first set of code, and then applies optimizations to the first set of code so as to generate a second set of code configured to operate efficiently with the ZOLB. The optimizations are designed to increase the number of loops of the first set of code that can be accommodated in the ZOLB, to further reduce the overhead of the loops placed in the ZOLB, and to eliminate redundant loading of the ZOLB. Optimizations for increasing the number of loops that can be accommodated in the ZOLB include, e.g., conditional instructions, loop splitting and function inlining. Optimizations for further reductions in loop overhead include, e.g., loop collapsing and loop interchange. Data flow analysis and loop peeling may be used to avoid redundant loading of the ZOLB.

Compiler optimization techniques for exploiting a zero overhead loop mechanism

A pipelined processor is configured to provide virtual single-cycle instruction execution using a register locking mechanism in conjunction with instruction stalling based on lock status. In an illustrative embodiment, a set of register locks is maintained in the form of a stored bit vector in which each bit indicates the current lock status of a corresponding register. A decode unit receives an instruction fetched from memory, and decodes the instruction to determine its source and destination registers. The instruction is stalled for at least one processor cycle if either its source register or destination register is already locked by another instruction. The stall continues until the source and destination registers of the instruction are both unlocked, i.e., no longer in use by other instructions. Before the instruction is dispatched for execution, the destination register of the instruction is again locked, and remains locked until after the instruction completes execution and writes its result to the destination register. The decode unit can thus dispatch instructions to execution units of the processor as if the execution of each of the instructions completed in a single processor cycle, in effect ignoring the individual latencies of the execution units. Moreover, the instructions can be dispatched for execution in a program-specified order, but permitted to complete execution in a different order.

Virtual single-cycle execution in pipelined processors

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A cooperative interconnection technique in accordance with the invention utilizes an inter-cluster move instruction specifying a source cluster and a destination cluster to copy a value from the source cluster to the destination cluster. The value is transmitted over a designated interconnect structure within the processor, and the inter-cluster move instruction is separated into two sub-instructions, one of which is executed by a unit in the source cluster, and another of which is executed by a unit in the destination cluster. These units may be, e.g., augmented ALUs or dedicated interface units within the clusters.

Cooperative interconnection for reducing port pressure in clustered microprocessors

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.

Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor

The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.

Compiler-controlled dynamic instruction dispatch in pipelined processors

A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. The processor further includes a datapath which is at least partially shared by the stack and register file, a multiplexer operative to select an output of either the stack or the register file for application to an input of the shared datapath, and a demultiplexer operative to select an output of the shared datapath for application to an input of either the stack or the register file. A program executed by the processor selects one of the storage spaces using, for example, a tag bit associated with a given instruction and indicating which of the storage spaces is to be used with that instruction, or a branch machine view (bmv) instruction which generates a control signal operative to select the given one of the storage spaces.

Shared datapath processor utilizing stack-based and register-based storage spaces

The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e.g., a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.

File replication methods and apparatus for reducing port pressure in a clustered processor

A system for debugging the computer program present in read-only memory (ROM) contains a debugger, a processor, read-only memory, a bus and a hardware debugging support module. The hardware debugging support module contains a first register called the range start register, a second register called the range end register and a comparator. The debugger uses a list of &ldquo;n&rdquo; user specified break points to divide a computer program into &ldquo;n&plus;1&rdquo; regions, each of which has a start address and an end address. The first register and the second register of the hardware debugging support module are programmed with the start address and end address of a region which contains a specific address. The comparator is connected to the first register and second register of the hardware debugging support module and is also connected to the bus which connects the read-only memory to the processor. The comparator monitors addresses traveling on the bus and causes the hardware debugging support module to interrupt the processor and transfer control of the computer program to the debugger if a specific address traveling on the bus does not fall within the range defined by the first register and the second register. The debugger then searches the remaining &ldquo;n&plus;1&rdquo; regions to see if the specific address lies within a second region. If such a region is found, then the start address and end address of that second region are entered into the first register and the second register and the computer program is run. However, if such a region is not found, then the computer program has reached a break point and the debugger transfers control of the program to the user. The computer program can then be single stepped to execute the instruction at which the break point was placed to obtain an output address. The start address and end address of the region that contain this output address are programmed into the first register and the second register and the computer program is run. This process is repeated until the entire computer program has been executed.

System for debugging (N) break points by dividing a computer program to (n&plus;1) regions each contains no break point and using two registers to define the start and end addresses of each region

A computer system supporting N different machine views, where N.gtoreq.2, includes a memory for storing instructions, a number of execution units for processing data based on execution controls, and N different decoders for generating the execution controls using instructions retrieved from the memory. Each of the N decoders is operative to decode retrieved instructions in accordance with one of the N machine views. A particular one of the N decoders to be used to decode a given retrieved instruction may be selected by a program running on the system. In one embodiment, the decoders for the N machine views are implemented as N separate decoders, and a multiplexer is used to select the output of one of the N decoders for connection to one or more of the execution units. In another embodiment, a set of reconfigurable hardware is dynamically reprogrammed to implement one or more of the N decoders as directed by the program running on the system.

Growing community of inventors

Bethlehem, PA, United States of America

Sanjay Jinturkar