Intel Corporation

Cisco Technology, Inc.

Riverstone Networks, Inc.

Sanjay Jain

Abhijit Patra

Nagaraj Bagepalli

Rina Panigrahy

Deepak J Aatresh

Daniel Yu-Kwong Ng

Jackie Liu

Lakhinder Walia

Gregory Scott Mathews

Romulus Pereira

The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.

Programmable packet parsing processor

A system and a method for managing forwarding table lookups and updates involve maintaining a first forwarding table in a first memory and a second forwarding table in a second memory, and then utilizing the first forwarding table to forward packets while the second forwarding table is updated with current route entries. The second forwarding table is updated in the background and therefore conventional CPU speeds do not cause performance problems. Once the second forwarding table is completely updated, a forwarding table pointer is switched and the second forwarding table is utilized to forward packets while the first forwarding table is updated. Because the second forwarding table has been completely updated in the background, switching the forwarding table pointer causes newly arriving packets to be forwarded according to a forwarding table that is free of inconsistencies.

Method and system for managing forwarding tables

A method and a system for controlling data flow through a network device involve regulating a first flow of network traffic with a first traffic control rule, regulating a second flow of network traffic with a second traffic control rule, and then regulating the passed portion of the two flows with a third traffic control rule that is generic to both the first flow and the second flow. The third traffic control rule regulates the passed portions of the first flow and the second flow on an aggregate basis, such that the total amount of traffic passed by the third traffic control rule does not exceed a predefined bandwidth limit. By regulating the bandwidth consumption of a group of flows with at least two levels of traffic control rules, bandwidth consumption can be simultaneously controlled for narrowly defined flows and more broadly defined flows.

Method and system for controlling data flow through a multiport switch

A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.

Power management for low power processors through the use of auto

An innovative protocol and system for implementing the same enables quick release of the bus by the master device, such as a CPU, to permit slave devices access to the bus. In one embodiment, the arbiter can select between the original hold protocol and quick hold protocol according to predetermined criteria which indicates that a low latency response is requested. Upon assertion of a QHOLD signal, the CPU issues a burst last signal to prematurely terminate outstanding burst transactions on the bus in a manner transparent to the slave devices. Once the outstanding bus cycles are complete, the CPU performs an internal backoff to immediately release the bus for access by the slave device requesting access. Any pending burst cycles which were terminated prematurely by the QHOLD signal, are subsequently restarted for the data not transacted by the CPU after the slave device completes access to the bus. The internal backoff mechanism is similarly transparent to the slave devices and does not cause a backoff signal to be issued to the peripherals or devices coupled to the bus. Thus, the addition of a quick hold protocol is added without significant modification of the slave devices' bus interface.

Growing community of inventors

Santa Clara, CA, United States of America

Sanjay Jain