Mentor Graphics Corporation

Cadence Design Systems, Inc.

Sanjay Gupta

Charles W Selvidge

Krishnamurthy Suresh

Suresh Krishnamurthy

Praveen Shukla

Deepak Kumar Garg

John R Stickley

Ronald James Squiers

Saurabh Khaitan

Satish Kumar Agarwal

Russell Elias Vreeland, Iii

Amit Jain

Saurabh Gupta

Mukesh Kumar Gupta

Sudhanshu Jayaswal

Tarun Beri

Utpal Bhattacharya

Vipul Kulshrestha

Ankit Garg

Jeffrey Evans

Abhijit Das

Mohd Vaseem

Yogesh Badaya

Kingshuk Banerjee

Jyotirmoy Daw

Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.

Bandwidth test in networking System-on-Chip verification

Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Latency test in networking system-on-chip verification

A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry. The system employs a backpressure flow control independent of the communication protocol, which can cause the traffic generation device to suspend sending messages when one or more message buffers in the traffic generation device, the reconfigurable hardware modeling device, or both cannot accept more messages based on predetermined conditions.

Flow control in networking system-on-chip verification

Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the reconfigurable hardware modeling device. Based on the traffic-shaping information, the ingress signal-level messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device.

Traffic shaping in networking system-on-chip verification

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.

Target capture and replay in emulation

Aspects of the disclosed technology relate to techniques for modeling content-addressable memory in emulation and prototyping. A model for content-addressable memory comprises memory circuitry configured to store match results for various search keys. The match results are stored in the second memory circuitry during write operations. The model for content-addressable memory may further comprise additional memory circuitry configured to operate as a standard computer memory, performing read operations alone and write operations along with the memory circuitry.

Content addressable memory modeling in emulation and prototyping

Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.

Low power corruption of memory in emulation

Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.

Hybrid compilation for FPGA prototyping

Aspects of the invention relate to techniques for dynamic control of design clock generation in emulation. A circuit design for verification is analyzed to determine one or more clock-enabling functions for a specific clock signal. Logic for generating a clock status signal based on the one or more clock-enabling signals is then determined. The clock status signal is employed to control clock generation in an emulation system for emulating the circuit design.

Dynamic control of design clock generation in emulation

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.

Modeling memory in emulation based on cache

Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.

Debug environment for a multi user hardware assisted verification system

The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected.

Third party component debugging for integrated circuit design

Aspects of the invention relate to techniques for using retiming to reduce circuit switching activity. Switching activity values at output ports of circuit elements of a circuit design are first computed based on switching activity values at input ports of the circuit elements and scaling factors associated with the circuit elements. Based on the switching activity values at the output ports of the circuit elements, one or more regions of the circuit design for retiming are identified. Retiming location information is then determined for the one or more regions. Finally, the identified one or more regions are then retimed to reduce switching activity based on the retiming location information.

Switching activity reduction through retiming

Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions.

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Noida, India

Sanjay Gupta