Synopsys, Inc.

Sanjay Gulati

Rajarshi Mukherjee

Bhaskar Pal

Shekaripuram V Venkatesh

Sauresh Bhowmick

Sourasis Das

Nitin Sharma

Kaushik De

David L Allen

Manish Goel

Nishant Patel

Malitha Kulatunga

Sachin Bansal

Parul Bhatia

Gaurav Pratap

Vishal Keswani

Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Automated root-cause analysis, visualization, and debugging of static verification results

State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

State table complexity reduction in a hierarchical verification flow

A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint. When a user modifies a module, the HPVS need only verify the changed module and related modules at higher levels of module hierarchy.

System and method for hierarchical power verification

A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction. A user interface allows display of identified power verification failures and may include an input device for facilitating correction of at least one of the electronic circuit design and the power intent file.

System and method for power verification using efficient merging of power state tables

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New Delhi, India

Sanjay Gulati