Synopsys, Inc.

Mentor Graphics Corporation

Other

Sanjay Dhar

Kok Kiong Lee

Aiqun Cao

Vishal Khandelwal

Yiu-Chung Mang

Laurence W Grodd

Robert L Walker

John G Ferguson

Prashant Saxena

Lin Yuan

Sanjay V Kumar

Joseph D Sawicki

Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.

Concurrent optimization of timing, area, and leakage power

Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis.

Look-up based buffer tree synthesis

Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing.

Automatic clock tree routing rule generation

Look-up based fast logic synthesis

Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.

Incremental clock tree synthesis

Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Manufacturability

An EDA tool is provided with a circuit simulator that simulates circuit operation using dynamic partitioning and on-demand evaluation. The circuit simulator includes a static partitioner, a dynamic partitioner and an evaluation scheduler. The static partitioner pre-forms a number of static partitions for the circuit. During simulation, the dynamic partitioner forms and re-forms a number of dynamic partitions referencing the static partitions. At each simulation time step, the evaluation scheduler determines which, if any, of the dynamic partitions have to be evaluated, and evaluating on-demand only those where evaluations are necessary. In one embodiment, when evaluations are performed, they are performed through matrix solution when accuracy is needed.

Circuit simulation using dynamic partitioning and on-demand evaluation

A switch level simulator having switch level speeds with near the accuracy of a circuit level simulator. Circuit parameters such as peak current, delay, and charge are calculated by using a dynamic short-circuit ratio. In the preferred embodiment a computer having a processor and memory is used to run the circuit simulations. A lookup table is built which represents how the circuit parameters vary with a change in the dynamic short-circuit ratio. The dynamic short-circuit ratio is calculated by taking the ratio of a first resistance in a first circuit path switching OFF to a second resistance in a second circuit path switching on. The circuit paths might be a parallel or series set of transistors which need to be combined to form an effective resistance for each path. The calculated dynamic short-circuit ratio is then used in the lookup table to determine the parameters in question.

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Lake Oswego, OR, United States of America

Sanjay Dhar