Atrenta, Inc.

Sanjay Churiwala

Bhanu Kapoor

Debabrata Bagchi

Joy Banerjee

A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits

Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits

Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.

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Noida, India

Sanjay Churiwala