Qualcomm Incorporated

International Business Machines Corporation

Resolve Therapeutics, LLC

Sanjay Bhikhubhai Patel

Jeffrey Todd Bridges

Yeshwant Nagaraj Kolla

Gabriel Martel Tarr

Carl Alan Waldspurger

James Norris Dieffenderfer

Harold Wade Cain, Iii

Ryan Donovan Wells

Brian William Curran

Burt Lee Price

Shivam Priyadarshi

Tin-Chee Lo

William Wu Shen

Matthew A Krygowski

Derek Robert Hower

James Arthur Posada

Nathan Samuel Nunamaker

Praduemn K Goyal

Clint Wayne Mumford

Craig Anthony Farrell

Shraddha Sridhar

Chris Gabel

Kaushal A Thakker

Anand Krishnamurthy

Lakshmikant Mamileti

Frank P Cartman

Raju P Kattady

SeyedMajid Zahedi

Chih Kang Lin

Sandy N Luu

Weihong Yu

The invention provides for optimized binuclease fusion proteins with increased pharmacokinetic properties. The optimized binuclease fusion proteins of the invention two or more nuclease domains (e.g., RNase and DNase domain) operably coupled to an Fc domain. The invention also provides methods of treating or preventing a condition associated with an abnormal immune response.

Optimized binuclease fusions and methods

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements

Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption are provided. In one aspect, an adaptive voltage modulation circuit detects a supply voltage droop by detecting when a supply voltage falls below a droop threshold voltage, and adjusts a clock signal provided to a load circuit in response to a supply voltage droop. The adaptive voltage modulation circuit keeps a count of the number of clock signal cycles during which the supply voltage is below the droop threshold voltage. The adaptive voltage modulation circuit increases the supply voltage in response to the count exceeding an upper threshold value, and decreases the supply voltage in response to the count being less than a lower threshold value at an end of a defined period. The adaptive voltage modulation circuit can reduce the time a load circuit operates with reduced frequency while minimizing power consumption.

Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption

A method, system, and/or computer program product improves an operation of an enterprise network. One or more processors receive an electronic request for delivery of a legacy component to an enterprise network of an enterprise. The processor(s) determine whether an upgrade component is available to the enterprise to replace the legacy component in the enterprise network based on predetermined request throttling parameters set by a receiver of the electronic request. The processor(s), in response to determining that the upgrade component is available to the enterprise, query a hardware sensor in the enterprise network for a sensor reading that indicates whether the upgrade component is compatible with an architecture of the enterprise network. The processor(s), in response to determining that the sensor reading indicates that the upgrade component is compatible with the enterprise network, reconfigure the enterprise network by an electronic installation of the upgrade component into the enterprise network.

Selective service redirection for telecom service migration

Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

Circuits, systems and methods to detect and accommodate power supply voltage droop

Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.

Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media

A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.

Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Method and apparatus for testing data steering logic for data storage having independently addressable subunits

A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.

Memory access system including a memory controller with memory redrive

Growing community of inventors

Cary, NC, United States of America

Sanjay Bhikhubhai Patel