Lsi Logic Corporation

Sanjay Adkar

Vilas V Gupte

Christian Joly

Zarir B Sarkari

Ravichandran Ramachandran

Sarika Agrawal

A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider. Since all the information that is needed by a synthesizer is available in the synthesis shell in netlist form, the shell is extremely accurate. The synthesis shell as mentioned above comprises a gate level description which is a subset of the synthesized block. This description is reduced by deleting elements of the gate level description according to a set of pre-specified criteria.

Synthesis shell generation and use in ASIC design

Systems and methods of verifying the design of the ASIC during design and implementation phases are provided. The ASIC design is verified utilizing information from a system simulation in the customer's system environment. During system simulation, the invention captures 'golden' vectors that may be used to test the ASIC during stand-alone simulation. The outputs generated by the ASIC during stand-alone simulation are compared to the outputs generated during the system simulation. Thus, the customer's system simulation is reproduced without having to reproduce the customer's system environment which allows the operation of the ASIC to be verified during various states of synthesis. Additionally, the test bench for testing the ASIC in stand-alone simulation is automatically generated eliminating the need for the user to manually generate a test bench.

System simulation for testing integrated circuit models

Methods and systems of automatically generating synthesis scripts and hierarchical flow/connectivity diagrams are provided. The user inputs design constraints, clock characteristics, technology files, and HDL code. The system handles cores, megafunctions, hardmacs, and black boxes appropriately for synthesis. During synthesis, individual modules in the HDL code may change. The system manages these incremental changes by generating incremental scripts which 1) compile, map and model the modules that have been changed and 2) characterize, compile and model the modules that have been changed in the hierarchy under that instance. During the iterative design process, new hierarchical flow diagrams may be generated to understand the full effect of the incremental changes.

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Saratoga, CA, United States of America

Sanjay Adkar