Micron Technology Incorporated

Intel Corporation

Other

Lodestar Licensing Group LLC

Sanh D Tang

John K Zahurak

Haitao Liu

Gordon A Haller

Gurtej S Sandhu

Martin Ceredig Roberts

Michael P Violette

Robert James Burke

Kamal M Karda

Scott E Sills

Wolfgang Mueller

Srinivas Pulugurtha

Kuo-Chen Wang

Sourabh Dhir

Akira Goda

Krishna Kumar Parat

Nishant Sinha

Hong Li

Roger W Lindsay

Chandra V Mouli

Litao Yang

Yunfei Gao

Durai Vishak Nirmal Ramaswamy

David H Wells

Tuman Earl Allen, Iii

Justin B Dorhout

Ming Zhang

Guangyu Huang

Lars P Heineck

Song Guo

Daniel M Smith

Richard J Hill

Anand Srinivasan

Deepak Chandra Pandey

Farrell Martin Good

Silvia Borsari

Werner Juengling

John A Smythe

Si-Woo Lee

Janos Fucsko

Mitsunari Sukekawa

Kris K Brown

Prashant Raghu

Michel Koopmans

Brent D Gilgen

Diem Thy N Tran

Venkatesan Ananthan

Fredrick David Fishburn

Nicholas R Tapias

Raj Narasimhan

Kunal R Parekh

Mark E Tuttle

Guy T Blalock

Ravi T Iyer

Jigish D Trivedi

Lifang Xu

Fred D Fishburn

Suraj J Mathew

Robert J Hanson

Yi Fang Lee

Robert B Kerr

Shih-Fan Kuan

Daniel Doyle

Sangmin Hwang

Andrew Li

Keith R Cook

Howard E Rhodes

Jun Liu

Kirk D Prall

Roy Edward Meade

Christopher John Kawamura

Mark Fischer

Yushi Hu

David K Hwang

Ceredig Roberts

Andrew M Bayless

Xiaonan Chen

Alex J Schrinsky

Chih-Chen Cho

Rajesh N Gupta

Alessandro Torsi

Guangjun Yang

Ramanathan Gandhi

Randal W Chance

Russell A Benson

Steven D Cummings

Katsumi Koge

Muralikrishnan Balakrishnan

Shen Hu

Paul Grisham

Naoyoshi Kobayashi

Shivani Srivastava

Kurt D Beigel

John K Lee

Rita J Klein

Shyam Surthi

Christopher W Petz

Sanjeev Sapra

Shane J Trapp

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.

Methods of utilizing etch-stop material during fabrication of capacitors, integrated assemblies comprising capacitors

A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

String driver assemblies including two-dimensional materials, and related memory devices

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Three dimensional memory and methods of forming the same

A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Driver placement in memories having stacked memory arrays

Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having voids along regions of gates, and methods of forming conductive structures

Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

Transistor structures having conductive structures along pillars of semiconductor material

Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

Methods of forming integrated assemblies having conductive material along sidewall surfaces of semiconductor pillars

Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

Microelectronic devices including two-dimensional materials, and related memory devices and electronic systems

A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

Apparatuses including elongate pillars of access devices

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

Memory arrays

Growing community of inventors

Boise, ID, United States of America

Sanh D Tang