Samsung Electronics Co., Ltd.

Sangyong Kim

Sechung Oh

Jungsik Park

Sangjin Hyun

Hoonjoo Na

Dongsoo Lee

Whankyun Kim

Jaeyoung Shin

Wonkeun Chung

Jae-Jung Kim

Jinkyu Jang

Byounguk Yoon

Hyunju Hong

Sehwan Choi

Sang Hwan Park

Woongeun Kwak

Kiwoong Kim

Youngman Jang

Seungwon Oh

Yongsung Park

Jinwoo Kim

Woojin Kim

Joonmyoung Lee

Kilho Lee

Woo Chang Lim

Kyungtae Nam

Byounghoon Lee

Youngsoo Chun

Dohun Cha

Kwonho Song

Seongeun Kim

Dae Sin Kim

Soonoh Park

Yonghee Park

Seungkyu Kim

Heejun Ryu

Jeongheon Park

Dong-Gwan Shin

Joohyung You

Taewon Sun

Bongchoon Park

Bosung Choi

Chanhyeong Lee

Jaejung Kim

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.

Semiconductor device and method of fabricating the same

A semiconductor device includes a first active region on a substrate, channel layers disposed on the first active region to be spaced apart from each other in a vertical direction, a first gate structure disposed on the first active region and surrounding each channel layer, and a first source/drain region on the first active region on at least one side of the first gate structure. The channel layers include first to third channel layers. The first gate structure includes a first gate electrode and a first gate dielectric layer. The first gate dielectric layer includes first to third portions surrounding the first to third channel layers, respectively. The second portion has a thickness greater than a thickness of the first portion, and the third portion has a thickness greater than the thickness of the second portion.

Semiconductor device having channel layers spaced apart in vertical direction

An electronic device is provided. The electronic device includes a board including a first conductive line, a second conductive line, a ground plane, and a conductive via hole connecting the first conductive line and the ground plane, at least one electronic component disposed in the board, an insulation member covering the at least one electronic component, and a conductive layer, the conductive layer includes a first part formed on a surface of the insulation member, a second part extending from an edge of the first part and electrically connected to the first conductive line, and a third part spaced apart from the second part and electrically connected to the second conductive line, and the electronic device includes at least one transmission line constituted by the second conductive line and the third part of the conductive layer.

Board having conductive layer for shielding electronic component and electronic device including the same

A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Semiconductor devices

A multiple display device with a number of display areas, and a method of operating the device are provided. The method includes: executing a first application, and displaying the first user interface on the first image-display area; displaying text or icons related to the second application on the third image-display area; receiving a first user input for selecting an item or action via the first image-display area; receiving, after receiving the first user input, a second user input for selecting the text or the icon via the third image-display area; and displaying the second user interface on the second image-display area, in response to the second user input, and processing the item or action, using the second application. Various embodiments are provided.

Multiple display device and method of operating the same

Provided are an electronic device and method for controlling functions of the electronic device according to attachment of an external device. The electronic device includes an interface part that electrically contacts an external device, and a processor that determines, when an external device is electrically connected, whether the external device has a second power source, and controls usage of a first power source of the electronic device according to a result of the determination.

Electronic device and method for controlling functions thereof according to attachment of external device

A method of controlling the output according to a type of connector and an electronic device adapted to the method are provided. The method includes determining whether a first, second and third external connector is inserted into a receptacle, via a circuit connected to the receptacle, wherein the receptacle is configured to receive the first, second or third external connector, each of the first and second connector includes a first number of contacts, and the third external connector includes a second number of contacts less than the first number of contacts; providing an audio output signal to the first external connector in a first manner when the first external connector is inserted into the receptacle; providing an audio output signal to the second external connector in a second manner which differs from the first manner when the second external connector is inserted into the receptacle; and providing an audio output signal to the third external connector in a third manner which differs from the first and second manners when the third external connector is inserted into the receptacle.

Method and apparatus for controlling output based on type of connector

Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50&#xb0; K to about 300&#xb0; K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.

Method and processing apparatus for fabricating a magnetic resistive random access memory device

Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment.

Magnetic memory devices having perpendicular magnetic tunnel structures therein

A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.

Magnetic memory devices including oxide multiferroic material

A magnetic memory device according to embodiments includes a first reference magnetic layer on a substrate, a second reference magnetic layer on the first reference magnetic layer, a free layer between the first reference magnetic layer and the second reference magnetic layer, a first tunnel barrier layer between the first reference magnetic layer and the free layer, and a second tunnel barrier layer between the second reference magnetic layer and the free layer. The first reference magnetic, second reference magnetic and free layers each have a magnetization direction substantially perpendicular to a top surface of the substrate. A resistance-area product (RA) value of the first tunnel barrier layer is greater than that of the second tunnel barrier layer.

Magnetic memory devices

Growing community of inventors

Suwon-si, South Korea

Sangyong Kim