Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Ajou University Industry-Academic Cooperation Foundation

Naver Corporation

Seoul National University

Sangwook Kim

Jinseong Heo

Yunseong Lee

Sanghyun Jo

Shihwa Lee

Dohyung Kim

Junghoe Kim

Taehwan Moon

Kwanghee Lee

Hyangsook Lee

Sunil Kim

Seunggeol Nam

Jaechul Park

Changjung Kim

Hagyoul Bae

Miyoung Kim

Ennmi Oh

Yangseock Seo

Donghyeok Choi

Rakesh Taori

Yongsang Yun

Changryong Heo

Seungnyun Kim

Kyongtae Han

Misun Park

Hosang Sung

Seongyeong Park

Miao Lei

Kyungsang Cho

Kangeun Lee

Seunghune Yang

Hyunseok Shin

Jeonga Shin

Ihun Song

Hiroshi Fujita

Pilsoo Kang

Sanghun Kim

Sujin Kim

Junghyun Park

Yong-Seok Park

Dongho Kim

Kyung-Eun Byun

Younghoon Kim

Jumin Chi

Keunwook Shin

Eunmi Oh

Jaeho Choi

Jiyoung Park

Sunghye Yoon

Eunsuk Kwon

Youngsoo Park

Sungwoo Lee

Sangchul Ko

Kyunghoon Cho

Jungho Kim

Soo-Young Jang

Sooyong Lee

Youngtae Kim

Jeanie Jung

Daedong Park

Jinkyu Jeong

Sung-Won Jeong

Seongwoon Choi

Jaewon Yang

Moonil Jung

Jeeyong Lee

Jeeeun Yang

Seongsoo Hong

Soohan Choi

Jehwan Lee

Joonwon Lee

Sohmann Kim

Heungsuk Oh

Jungmin Kim

Hwanju Kim

Jeeeun Jung

Kunsuk Kim

Woo-Yong Cho

Yeowon Yoon

Kihyun Yu

Sungyong Moon

Kyu-Bin Han

Changmook Yim

Yangwoo Heo

Dongcheol Hur

Yeong-Ho Jeong

Wonchan Lee

Junghoo Kim

Donyung Kim

Jin-sun Choi

SungSoo Suh

Youngchang Kim

Sukjoo Lee

YongJin Chun

Youngkou Han

Kyungjik Lee

Sukhoon Noh

Kyubin Han

Provided is a method of fabricating a semiconductor device using a curvilinear OPC method. The method of fabricating the semiconductor device includes performing an optical proximity correction (OPC) step on a layout to generate a correction pattern, the correction pattern having a curvilinear shape, performing a mask rule check (MRC) step on the correction pattern to generate mask data, and forming a photoresist pattern on a substrate using a photomask, which is manufactured based on the mask data. The MRC step includes generating a width skeleton in the correction pattern, generating a width contour, which satisfies a specification of a mask rule for a linewidth, from the width skeleton, and adding the correction pattern and the width contour to generate an adjusting pattern.

Method of fabricating semiconductor device

Disclosed herein is a thin film structure, including a first conductive layer on a dielectric layer including a plurality of layers. Each of the plurality of layers includes a dopant layer containing a dopant A and a HfOlayer to form a compound of HfAO(0<x<1, z is a real number). An uppermost layer of the plurality of layers is thickest among the plurality of layers. The first conductive layer contacts the uppermost layer.

Thin film structure and electronic device including the same

Disclosed are a thin film structure and an electronic device including the same. The disclosed thin film structure includes a dielectric material layer between a first material layer and a second material layer. The dielectric material layer includes a dopant in a matrix material having a fluorite structure. The dielectric material layer is uniformly doped with a low concentration of the dopant, and has ferroelectricity.

Thin film structure including dielectric material layer and electronic device employing the same

An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.

Integrated circuit including transistors and a method of manufacturing the same

Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Ferroelectric thin-film structure and electronic device including the same

Provided is a method for providing augmented content, wherein whether a user terminal is located in a preset unit space is determined on the basis of the location of the user terminal, and if the user terminal is determined to be located in the unit space, an image captured by a camera is displayed through an augmented reality (AR) view by being augmented with content associated with the unit space.

Method and device for providing augmented content through augmented reality view on basis of preset unit space

A position recognition method and a system based on visual information processing are disclosed A position recognition method according to one embodiment including the steps of: generating a frame image through a camera; transmitting, to a server, a first global pose of the camera and the generated frame image; and receiving, from the server, a second global pose of the camera estimated on the basis of a pose of an object included in the transmitted frame image.

Position recognition method and system based on visual information processing

Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Electronic device and method of manufacturing the same

A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Domain switching devices and methods of manufacturing the same

A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a layout and forming a photoresist pattern on a substrate using a photomask that is manufactured with the layout corrected by the OPC operation. The OPC operation includes sectioning the layout into a low-level patch and a high-level patch, performing a first OPC operation on the low-level patch, the first OPC operation including generating a first boundary correction pattern of a curvilinear shape on a boundary between the low-level patch and the high-level patch, performing a second OPC operation on the high-level patch, the second OPC operation including a second boundary correction pattern of a curvilinear shape on the boundary, and conforming the first boundary correction pattern and the second boundary correction pattern to each other to generate a conformed boundary correction pattern of a curvilinear shape.

Optical proximity correction method and method of fabricating a semiconductor device using the same

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

Complementary metal oxide semiconductor device

A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

Semiconductor device including ferroelectric material, neuromorphic circuit including the semiconductor device, and neuromorphic computing apparatus including the neuromorphic circuit

A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Ferroelectric structure including a ferroelectric film having a first net polarization oriented toward a first polarization enhancement film and semiconductor device including the same

The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Oxide semiconductor transistor, method of manufacturing the same, and memory device including oxide semiconductor transistor

A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

Ferroelectric thin-film structures, methods of manufacturing the same, and electronic devices including the ferroelectric thin-film structures

Growing community of inventors

Seoul, South Korea

Sangwook Kim