Samsung Electronics Co., Ltd.

Sangwoo Pae

Hwasung Rhee

Taeyoung Jeong

Jinsoo Bae

Hyunggyun Noh

Miji Lee

Yoonkyeong Jo

Hyun-Min Choi

Uihui Kwon

Hagju Cho

Keunho Lee

Seonhaeng Lee

Il-Joo Choi

Deok-Seon Choi

Yeoil Yun

Iljoo Choi

Deokseon Choi

Keunho Rhew

Gun-Hee Bae

Junekyun Park

Kyongtaek Lee

Jongwook Jeon

A semiconductor device includes a first fin pattern protruding from a substrate and extending in a first direction; first and second active layers extending in the first direction on the first fin pattern, the second active layer being at a level higher than a level of the first active layer, the first and second active layers forming a first active layer structure; a first gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, and extending in a second direction; and a second gate intersecting the first and second active layers, surrounding upper and lower surfaces and opposing side surfaces of each of the first and second active layers, extending in the second direction, and disposed to be parallel to the first gate. The first active layer includes a first region extending from a first overlapping region of the first active layer overlapping the first gate by a first length in a direction away from the second gate, and the second active layer includes a first region extending from a first overlapping region of the second active layer overlapping the first gate by a second length in a direction away from the second gate, the second length shorter than the first length.

Semiconductor device having different extending active layers

A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Semiconductor package including stacked chip structure

A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

Semiconductor package device

A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than &#x2153; of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than &#x2153; of the width of the top surface of the via.

Semiconductor device including via and wiring

A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.

Memory devices including one-time programmable memory cells

A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

Simulation system estimating self-heating characteristic of circuit and design method thereof

A semiconductor device includes: a semiconductor substrate; a plurality of conductive lines formed on the semiconductor substrate; and an electrode for temperature measurement. The electrode is connected to the plurality of conductive lines. An electronic device includes a semiconductor device and has a temperature sensing function. The semiconductor device includes: a semiconductor substrate; a plurality of conductive lines formed on the semiconductor substrate; and an electrode for temperature measurement.

Semiconductor devices including electrodes for temperature measurement

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Sangwoo Pae