Intel Corporation

Sangwoo Pae

Jack T Kavalieros

Robert S Chau

Suman Datta

Justin K Brask

Gilbert W Dewey

Matthew V Metz

Mark L Doczy

Markus Kuhn

Adrian B Sherrill

Jose A Maiz

Walid M Hafez

Chia-Hong Jan

Zhanping Chen

Anisur Rahman

Jie-Feng Lin

Chetan Prasad

A programmable anti-fuse element includes a substrate (), an N-well () in the substrate, an electrically insulating layer () over the N-well, and a gate electrode () over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element () includes a metal gate fuse () and an oxide anti-fuse () such as the programmable anti-fuse element just described.

Method of forming programmable anti-fuse element

A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.

Process charging and electrostatic damage protection in silicon-on-insulator technology

A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Method for making a semiconductor device having a high-k gate dielectric

A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 &#x212b; to 60 &#x212b;. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600&#xb0; C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

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Beaverton, OR, United States of America

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