Samsung Electronics Co., Ltd.

Sanguk Han

Hyoeun Kim

Sunkyoung Seo

JaeMin Jung

Taehwan Kim

Chajea Jo

Wonil Lee

Seunghoon Yeon

Yonghoe Cho

Hyunjung Song

Jeongkyu Ha

Yoonha Jung

KwanJai Lee

A chip on film (COF) package includes a base film having an upper surface and a lower surface opposite to each other, a bridge film having an edge that overlaps the base film, and an upper surface and a lower surface opposite to each other, a display driver integrated circuit (IC) mounted on the upper surface of the base film, and a heat dissipation member arranged in correspondence with the display driver IC on the lower surface of the base film. The upper surface of the base film and the lower surface of the bridge film adhere to each other in their respective long axis directions, and a long axis length of the bridge film is greater than a long axis length of the base film.

Chip-on-film package and display apparatus including the same

A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.

Chip on film package with trench to reduce slippage and display device including the same

A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

Semiconductor package

A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Chip-stacked semiconductor package and method of manufacturing same

A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased.

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Asan-si, South Korea

Sanguk Han