Samsung Electronics Co., Ltd.

Sangsu Kim

Junggil Yang

Taeyong Kwon

Sung Gi Hur

Jae-Hwan Lee

Mirco Cantoro

Shigenobu Maeda

Junbeom Park

Krishna Bhuwalka

Zhenhua Wu

Jungdal Choi

Changjae Yang

Dongkyu Lee

Seokhoon Kim

Byeongchan Lee

Jinyeong Joe

Seung Mo Ha

Sanghyuk Hong

Sunghil Lee

Chung Geun Koh

Myoungsun Ha

Kangmook Lim

Changhoon Kwak

Moonsub Kim

Wooseok Park

Daekwon Joo

In Joon Pyeon

Yunsang Shin

A semiconductor device includes a first source/drain structure having a first length in a horizontal direction, as viewed in a planar cross-sectional view, the horizontal direction being perpendicular to a vertical direction, a second source/drain structure having a second length in the horizontal direction, as viewed in the planar cross-sectional view, the second length being less than the first length, channels extending between the first source/drain structure and the second source/drain structure, the channels being spaced apart from each other in the vertical direction, at least one sacrificial pattern between adjacent ones of the channels, and a trench penetrating the channels and the at least one sacrificial pattern.

Semiconductor device

A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

Method of manufacturing a semiconductor device

Semiconductor devices

A light-emitting package including a substrate having pixel regions; first to third light-emitting chips on each of the pixel regions; and a molding layer on a top surface of the substrate, the molding layer covering the first to third light-emitting chips, wherein one of the first to third light-emitting chips emits light whose color is different from others of the first to third light-emitting chips, on pixel regions, the first to third light-emitting chips are arranged along a first direction, the first direction being parallel to the top surface of the substrate, a minimum interval between the first light-emitting chip and a top or side surface of the molding layer is different from a minimum interval between the second light-emitting chip and the top or side surface of the molding layer, the side surface of the molding layer intersects a second direction parallel to the top surface of the substrate.

Light-emitting package and display device including the same

A semiconductor device is provided including an active region on a substrate A plurality of channel layers is spaced apart on the active region. Gate structures are provided. The gate structures intersect the active region and the plurality of channel layers. The gate structures surround the plurality of channel layers. Source/drain regions are disposed on the active region on at least one side of the gate structures. The source/drain regions contact with the plurality of channel layers. A lower insulating layer is disposed between side surfaces of the gate structures on the source/drain regions. Contact plugs penetrate through the lower insulating layer. The contact plugs contact the source/drain regions. An isolation structure intersects the active region on the substrate and is disposed between the source/drain regions adjacent to each other. Each of the gate structures includes a gate electrode and a gate capping layer including materials different from each other.

Semiconductor devices including a gate isolation structure and a gate capping layer including different materials from each other

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

Semiconductor devices including field effect transistors and methods of forming the same

A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

Method of fabricating semiconductor device

A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between adjacent second regions; a plurality of first gate structures on the first regions of the semiconductor substrate; and a plurality of second gate structures on the second regions of the semiconductor substrate, wherein each of the first and second gate structures includes a lower gate structure including a recess region defined by sidewalls and a bottom connecting the sidewalls; and an upper gate structure including a gap-fill metal pattern that fills the recess region of the lower gate structure, wherein the bottom of the lower gate structure included in the first gate structure has a thickness different from a thickness of the bottom of the lower gate structure included in the second gate structure, and wherein the gap-fill metal patterns of the first and second gate structures have top surfaces at substantially a same level.

A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

Semiconductor device and method of fabricating the same

A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

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Yongin-si, South Korea

Sangsu Kim