Samsung Electronics Co., Ltd.

Stevens Institute of Technology

Sangrok Hah

Byunglyul Park

Juhyuck Chung

Hongseong Son

Jianjun Wei

Chankeun Park

Traugott E Fischer

A method for forming void-free, low contact-resistance damascene interconnects during a manufacturing process of an integrated circuit having both narrow and deep openings and wide and shallow openings on a same substrate features a two-step copper (Cu) deposition process, with a high-temperature rapid annealing process being conducted after the first deposition. After forming in a top surface a narrow and deep opening and a wide and shallow opening, a first copper (Cu) layer is deposited on a seed layer using a small-grained Cu material to completely fill the narrow and deep opening. After annealing the first Cu layer to reduce stress on the resulting structure, a second layer of large-grained Cu material is deposited on the annealed first Cu layer to fill the remainder of the openings. The resulting assembly, which requires no additional annealing, is then planarized to the original surface.

Method for creating a damascene interconnect using a two-step electroplating process

A method of polishing selected ceramics and metals is provided wherein the selected ceramic or metal material is rubbed against a solid surface in the presence of a nonabrasive liquid medium which only attacks the selected ceramic or metal material under friction. Examples of materials for the tribochemical polishing process includes ceramics such as silicon, silicon nitride, silicon carbide, silicon oxide, titanium carbide and aluminum nitride and metals such as tungsten. Both ceramic and metal surfaces can be polished, as in a damascene structure of an integrated circuit.

Tribochemical polishing of ceramics and metals

Growing community of inventors

Seoul, South Korea

Sangrok Hah