International Business Machines Corporation

Sangram Alapati

Satish Kumar Sadasivam

Prathiba Kumar

Varun Mallikarjunan

Rajan Ravindran

Brad Lee Herold

Puneeth A Bhat

Amit Dugar

Gowri Shankar Palani

Hima B Nimmagadda

Alexandru Adrian Patrascu

Nitin Kumar Gupta

Shakti Kapoor

Puneeth A H Bhat

Shruti Saxena

Jayakumar N Sankarannair

Harish P Omkar

An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.

Bandwidth aware resource optimization

Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.

Control of speculative demand loads

A system may include a memory to store an enhancer to identify a branch instruction, having a miss-prediction rate above a threshold, in an executing thread. The system may additionally include an instruction update unit to modify an operation code (opcode) of the branch instruction, where a modified opcode of a branch instruction indicates an instruction fetch priority for an executing thread. The system may further include a processor, having an instruction decode unit to set a modified instruction fetch priority of the first executing thread based on the modified opcode of the branch instruction, and an instruction fetch unit to retrieve instructions for the first executing thread from the instruction cache at a first rate, the first rate indicated by the modified instruction fetch priority of the first executing thread.

Hardware managed dynamic thread fetch rate control

A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.

Simultaneous multithreading resource sharing

A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.

Tightly-coupled context-aware irritator thread creation for verification of microprocessors

The present disclosure includes, but is not limited to, a method, system and computer-usable medium for improving performance measurement by analyzing the various events in a multiplexing counting mode and configuring the sampling time accordingly to more effectively performing the sampling. In certain embodiments, when groups of operations are identified for sampling, the present disclosure generates a time sampling table for these groups of operations. The time sampling table is dynamically altered during the runtime of the application to alter the sampling interval of each group. The sampling interval of each group can be increased or decreased based on a threshold of occurrence of the event. This disclosure provides more accurate performance measurement of important events and facilitates a determination of how important events impact application performance.

Smart multiplexing of performance counters for performance measurement

A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

Run-time task-level dynamic energy management

A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Validating cache coherency protocol within a processor

A system, and computer program product for cloud optimization using workload analysis are provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.

Cloud optimization using workload analysis

A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Effective validation of execution units within a processor

A method for cloud optimization using workload analysis is provided in the illustrative embodiments. An architecture of a workload received for execution in a cloud computing environment is identified. The cloud computing environment includes a set of cloud computing resources. A section of the workload is identified and marked for static analysis. Static analysis is performed on the section to determine a characteristic of the workload. A subset of the set of cloud computing resources is selected such that a cloud computing resource in the subset is available for allocating to the workload and has a characteristic that matches the characteristic of the workload as determined from the static analysis. The subset of cloud computing resources is suggested to a job scheduler for scheduling the workload for execution.

A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.

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Austin, TX, United States of America

Sangram Alapati