Yangtze Memory Technologies Co., Ltd.

Sangoh Lim

Hang Song

Gyuwan Kwon

Qiang Tang

A memory device includes an input/output (I/O) interface, a first buffer and a second buffer coupled to the I/O interface, and an input buffer controller coupled to the I/O interface. The input buffer controller is configured to in response to receiving a command signal or an address signal from the I/O interface, enable the first buffer to perform a command cycle or an address cycle, and in response to receiving a data signal from the I/O interface, enable the second buffer to perform a data cycle at a speed higher than the command cycle or the address cycle performed by the first buffer.

High-performance input buffer and memory device having the same

A method for operating a memory device includes receiving an input that includes a command signal, an address signal, and a data signal, transmitting the command signal or the address signal to a low speed buffer, and transmitting the data signal to a high speed buffer.

In certain aspects, a memory device includes an array of memory cells. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. A redundant bank of the M redundant banks is located between two main banks of the N main banks or adjacent to one main bank of the N main banks.

Memory device with failed main bank repair using redundant bank

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes a first-level memory unit which includes a plurality of second-level memory units. Each second-level memory unit includes N main banks and a redundant bank, where N is a positive integer. The I/O circuit is configured to direct N pieces of data to or from N working banks in a corresponding second-level memory unit. The I/O control logic is configured to determine the N working banks from the N main banks and the redundant bank in the corresponding second-level memory unit based on bank fail information indicative of a failed main bank of the N main banks and control the I/O circuit to direct the N pieces of data to or from the N working banks, respectively.

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is great than M. The I/O circuit is coupled to the N main banks and the M redundant banks and configured to direct N pieces of data to or from N working banks, respectively. The control circuit is configured to determine the N working banks from the N main banks and the M redundant banks based on bank fail information indicative of K failed main banks of the N main banks. The N working banks include K redundant banks of the M redundant banks, where K is a positive integer not greater than M. The control circuit is further configured to control the I/O circuit to direct K pieces of data of the N pieces of data to or from the K redundant banks, respectively.

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Wuhan, China

Sangoh Lim