Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Sangmin Kang

Hanvit Yang

Joong-Soo Moon

Kyungsik Kim

Jihoon Choi

Kyungwook Park

Yoongoo Kang

Dain Lee

Changwoo Seo

Kiyong Park

Suyoun Song

DooSub Choi

A method of fabricating an integrated circuit device includes forming on a semiconductor substrate a mold stack that includes a plurality of insulating layers and a plurality of mold layers alternately arranged. A mask pattern including an opening is formed on the mold stack. A channel hole is formed by removing the mold stack exposed through the opening. A sacrificial film is formed on a lateral wall of the mold stack exposed through the channel hole. An oxidation process is performed on the sacrificial film and the mold stack to convert the sacrificial film to a sacrificial oxide film. An etching process is performed to remove the sacrificial oxide film.

Method of fabricating integrated circuit device and method of fabricating electronic system having the same

A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

Semiconductor device

A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.

Vertical memory devices and methods of manufacturing the same

A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.

A circuit board assembly includes a flexible circuit board including a first surface, a second surface opposite to the first surface, sensing pads on the first surface, and a connector on the second surface, a first liner which includes a first rear surface covering a portion of the first surface and a first top surface that is opposite to the first rear surface and in which a first opening passing through the first rear surface from the first top surface is defined, a second liner which includes a second rear surface covering a portion of the second surface and a second top surface that is opposite to the second rear surface and in which a second opening passing through the second rear surface from the second top surface is defined. Each of the first and second openings is spaced apart from the flexible circuit board in a plan view.

Electronic panel assembly including circuit board assembly and method for manufacturing the same

A liquid crystal display device in which an inversion driving scheme is applied to a pixel array which shares data lines. The liquid crystal display device varies driving waveforms of gate signals or data signals according to temperature and may suppress a color deviation of a display panel attributable to inversion of polarities of data signals. A timing controller may be configured to apply control signals to a data drive circuit and a gate drive circuit, the control signals includes a slew rate control pulse that controls the data drive circuit to vary any one of a rising slew rate and a falling slew rate of the data signal corresponding to the main charge interval of each of the gate signals.

Growing community of inventors

Hwaseong-si, South Korea

Sangmin Kang