Samsung Electronics Co., Ltd.

Sungkyunkwan University

Northeastern University

Postech Research and Business Development Foundation

Sangjoon Kim

Seungchul Jung

Hyungwoo Lee

Sungmeen Myung

Yongmin Ju

Chisung Bae

Jaehong Jung

Hyunsoo Kim

Jung-Hoon Chun

Biao Wang

Boyoung Seo

Junyeub Suh

Xuetao Feng

Yoonmyung Lee

Kangho Lee

Soonwan Kwon

Hui Fang

Minje Kim

Jaeyoon Sim

HaiBing Ren

YongNan Ji

Jaehan Park

Hyunwoo Son

Jaehyeon Ryu

A neuromorphic device includes a plurality of resistor lines, each comprising a plurality of resistors that are serially connected to each other; one or more current sources configured to control a current flowing in each of the resistor lines to a respective current value; a plurality of capacitors configured to be electrically connected to each of the resistor lines and to sample respective voltage of each of the resistor lines representing results of neuromorphic operations; and a switch configured to connect the plurality of the capacitors in parallel after the sampling the respective voltage of each of the resistor lines, to output a sum of the results of neuromorphic operations.

Neuromorphic device and driving method thereof

A neural network apparatus performs multiply-accumulate (MAC) operations with respect to fractions of weights and input activations in a block floating-point format by using an analog crossbar array, performs addition operations with respect to shared exponents of weights and input activations in a block floating-point format by using a digital computing circuit, and outputs a partial sum of floating-point output activations by combining the result of the MAC operations and the result of the addition operations.

Neural network apparatus performing floating-point operation and operating method of the same

An implant system includes an electrode portion comprising plural electrodes to perform nerve stimulation and nerve sensing, an impedance controller configured to selectively connect the plural electrodes between a stimulator to perform nerve stimulation and a sensor to perform nerve sensing based on a control signal, and set an impedance of each of the plural electrodes, and a processor configured to control a contact impedance by the plural electrodes by generating the control signal to control at least one of plural switches connected respectively to the plural electrodes, or variable resistors connected respectively to the plural electrodes, based on at least one of a selectively set purpose of the plural electrodes or a position of an electrode to which nerve stimulation is to be provided.

Implant system and method

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

Processing device and electronic device having the same

A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.

A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.

Device and method with multi-bit operation

A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.

Method and apparatus performing operations using circuits

An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.

Apparatus and method with in-memory processing

An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

Apparatus and method with in-memory delay dependent processing

Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Processing device based on magnetic tunnel junction (MTJ) element and electronic system including the processing device

A method and apparatus for performing anomaly detection by using a neural network are provided. The apparatus is configured to extract input features of an input data signal, obtain output features of the neural network by processing the input features through the neural network, obtain an error based on the input features and the output features, and determine whether the input data signal indicates an abnormal signal based on the error and a threshold.

Method and apparatus for performing anomaly detection using neural network

Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.

Processing apparatus and electronic device including the same

An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; and a time-digital converter configured to perform time-digital conversion at the second time points.

An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.

Growing community of inventors

Hwaseong-si, South Korea

Sangjoon Kim