Samsung Electro-Mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Sangik Cho

Ju Ho Kim

Jong Eun Park

Jehyung Yoon

Dam Yun

Eun Sun Kim

Jin Uk Lee

Hiroki Okada

Hyun Seok Yang

Chan Jin Park

Mi Jeong Jeon

Haneul Kim

Young Ook Cho

In Jae Chung

Dongwoo Baek

Sunghoon Kim

Sung Woo Han

Jung Hyun Park

Dong Hoon Lee

Chi Won Hwang

Mi Geum Kim

Nam Keun Oh

Sang Hyun Ji

Young Hun You

Do Hwan Kim

Mi Jung Park

Doo Seub Shin

Jaekyu Kim

Kipyo Hong

Mi-Geum Kim

Hoseung Jang

Yong Su Lee

A printed circuit board includes: a first metal layer; an organic insulating layer covering at least a portion of the first metal layer and having a via hole exposing at least a portion of an upper surface of the first metal layer; a first seed metal layer disposed on an upper surface of the organic insulating layer; a second seed metal layer disposed on the first seed metal layer and extending onto a wall surface of the via hole and the exposed upper surface of the first metal layer; and a second metal layer disposed on the second seed metal layer and filling at least a portion of the via hole, wherein the first seed metal layer includes a first sputtering layer including titanium (Ti), and the second seed metal layer includes an electroless plating layer.

Printed circuit board

A multilayer ceramic capacitor may include a ceramic body, a plurality of first internal electrodes and a plurality of second internal electrodes disposed inside the ceramic body, a first external electrode disposed outside the ceramic body and connected to the plurality of first internal electrodes, and a second external electrode disposed outside the ceramic body and connected to the plurality of second internal electrodes, where the first external electrode may include, a first conductive carbon layer electrically connected to the plurality of first internal electrodes, and a first plated layer covering the first conductive carbon layer, and where the second external electrode may include, a second conductive carbon layer electrically connected to the plurality of second internal electrodes, and a second plated layer covering the second conductive carbon layer.

Multilayered ceramic capacitor

Disclosed is a DC-to-DC converter which includes a first switching circuit connected between a power line receiving a DC voltage and an output terminal of the DC-to-DC converter and switched based on a first pulse control signal, a second switching circuit connected between the output terminal and a ground and switched based on a second pulse control signal, a pulse control signal generation circuit that receives a first level of a first voltage associated with an output voltage and a second level of a first reference voltage, wherein, in response to the second level being higher than the first level, the pulse control signal generation circuit is configured to generate the first pulse control signal to increase the output voltage and wherein, in response to the second level being lower than the first level, the pulse control signal generation circuit is configured to generate the second pulse control signal.

DC-to-DC converter with pulse skipping function and on-time control function, and electronic devices including the same

A printed circuit board includes a first insulating layer, a first conductor-pattern layer disposed on one surface of the first insulating layer, a first recess formed in the other surface of the first insulating layer opposing one surface of the first insulating layer, a second conductor-pattern layer disposed in the first recess, and a first metal post penetrating the first insulating layer, connecting the first and second conductor-pattern layers to each other, and having one end exposed to a bottom surface of the first recess, wherein the second conductor-pattern layer includes a seed layer disposed on at least a portion of each of a surface of one end of the first metal post exposed to the bottom surface of the first recess and an internal surface of the first recess including the bottom surface of the first recess, and a plating layer disposed on the seed layer to fill at least a portion of the first recess.

A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors.

Method of manufacturing printed circuit board

A camera module includes: a first body including a substrate; an image sensor mounted on the substrate; a second body including a lens module; a ball bearing disposed between the first body and the second body to enable movement of the second body relative to the first body; and a driving member disposed between the first body and the second body to provide driving force to move the second body in at least one direction intersecting an optical axis.

Camera module with piezoelectric driving member

A voltage converter includes a converting circuit having an inductor connected to a switching node, a first switch element connected between the switching node and a ground voltage, and a second switch element connected between the switching node and an output node; and a switching control circuit configured to adjust a feedback voltage divided from an output voltage of the output node based on a current state of the inductor, and configured to generate switching control signals for charging the inductor with an input voltage and discharging a voltage charged in the inductor, based on a sensing signal based on a current of the inductor and the adjusted feedback voltage.

Voltage converter and power management device including the same

Voltage converter with feedback adjustment and power management device including the same

A antenna may include a first dielectric layer having a first surface and a second surface opposing the first surface; a second dielectric layer having a third surface, and a fourth surface opposing the third surface; an adhesive layer disposed between the second surface and the third surface and connecting the first dielectric layer to the second dielectric layer; a patch pattern disposed on the second surface and embedded in the adhesive layer; and a coupling pattern disposed on the fourth surface and having at least a portion overlapping the patch pattern on a plane. Each of the first dielectric layer and the second dielectric layer may include an organic binder and an inorganic filler.

Antenna

A printed circuit board includes an insulating layer, a circuit pattern embedded in the insulating layer and including a first metal layer, a second metal layer and a third metal layer disposed between the first metal layer and the second metal layer, and a connection conductor disposed on one surface of the insulating layer and connected to the circuit pattern, wherein the first metal layer is exposed through the one surface of the insulating layer.

An antenna includes a first dielectric layer having a first surface and a second surface, a second dielectric layer having a third surface and a fourth surface, and a reinforcing layer disposed between the first dielectric layer and the second dielectric layer and including an insulating material. A first adhesive layer is disposed between the first dielectric layer and the reinforcing layer, and a second adhesive layer is disposed between the second dielectric layer and the reinforcing layer. A first pattern layer is disposed on a surface of the first dielectric layer facing the first adhesive layer, and a second pattern layer is disposed on a surface of the second dielectric layer facing away from the second adhesive layer. The reinforcing layer has a first cavity penetrating a region between the first and second dielectric layers.

An antenna includes a first dielectric layer having a first surface and a second surface opposing the first surface; a second dielectric layer having a third surface, and a fourth surface opposing the third surface; a third dielectric layer having a fifth surface and a sixth surface opposing the fifth surface; a first adhesive layer disposed between the second surface and the third surface; a second adhesive layer disposed between the fourth surface and the fifth surface; a patch pattern disposed on the second surface and embedded in the first adhesive layer; a first coupling pattern disposed on the fourth surface and embedded in the second adhesive layer, and a second coupling pattern disposed on the sixth surface. The patch pattern, the first coupling pattern, and the second coupling pattern at least partially overlap one another on a plane.

Growing community of inventors

Suwon-si, South Korea

Sangik Cho