Samsung Electronics Co., Ltd.

Sanghoon Myung

Changwook Jeong

Min-Chul Park

Hyunjae Jang

In Huh

Jisu Ryu

Hyeon Kyun Noh

Wonik Jang

Hyungtae Kim

Jinwoo Kim

Sunghee Lee

Yongwoo Jeon

Jeonghoon Ko

Kanghyun Baek

Yunrong Li

Min Chul Jeon

According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

Simulation method for semiconductor fabrication process and method for manufacturing semiconductor device

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Simulation system for semiconductor process and simulation method thereof

A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

Non-transitory computer-readable medium storing program code generating wafer map based on generative adversarial networks and computing device including the same

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Semiconductor fault analysis device and fault analysis method thereof

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Goyang-si, South Korea

Sanghoon Myung