Lg Display Co., Ltd.

SangHee Yu

SungHyun Cho

Byoungwoo Kim

SangWoon Kim

Hun Jeoung

SangGul Lee

Sungwook Chang

DongSoo Kim

BoSun Lee

Hoon Choi

NamSu Kim

Taesang Kim

YeonTaek Yoo

Heonkwang Park

SukHo Cho

GwangTae Kim

HyunJin Shin

HwaChun Lim

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Array substrate

In an exemplary embodiment of the present disclosure, a thin film transistor including a gate electrode, an active layer, a source electrode, and a drain electrode on a non-pixel area of a substrate includes a first insulating layer that insulates the gate electrode from the source electrode and the drain electrode, and a second insulating layer that covers the source electrode and the drain electrode. According to an exemplary embodiment of the present disclosure, the first insulating layer and the second insulating layer are configured so as not to be extended to a pixel area of the substrate in order to reduce possible oscillation of transmittance depending on a viewing angle which occurs when a specific light of a light source passes through the pixel area.

Thin film transistor and display device

Array substrate and display device

A display device according to an embodiment includes a lower substrate in which a display area and a non-display area are divided and an upper substrate which corresponds to the lower substrate and includes a black matrix BM. Further, the display device can include a bezel which is located on the non-display area and includes a GIP driver, a plurality of signal transmission lines, a connection line connecting the GIP driver and the plurality of signal transmission lines, and a seal area equipped with a sealant, in a direction being apart from one side of the display area, a plurality of bridge patterns which is located on the non-display area and electrically connects the GIP driver and the connection line, and the connection line and the plurality of signal transmission lines, respectively, and a plurality of shield patterns enclosing the plurality of bridge patterns. Also, the display device can include a plurality of shield patterns which minimize an area in which the sealant and the plurality of bridge patterns are in directly contact with each other.

Narrow bezel display device

A touch recognition enabled display panel includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.

Display panel with conductive lines under thin-film transistors

A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.

Gate driver and display device including the same

A liquid crystal display panel includes features to prevent damage to the liquid crystal alignment layer when a color filter substrate and a thin-film transistor array substrate are moved relative to each other. The liquid crystal display panel may include a column spacer on the color filter substrate under the black matrix and a bump pattern on the array substrate where the column spacer and the bump pattern are in contact with each other. The array substrate may otherwise include a planarization layer with a step portion and a protective layer on the planarization layer where the protective layer is in contact with the column spacer.

Array substrate and liquid crystal display device including the same

A display panel and a method of driving the same are disclosed. The display panel includes a shift register with a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines. Each stage includes a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween, a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and a node controller coupled to the first node, the second node, and the output node. In each stage, the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.

Display panel having a node controller for discharging nodes in a scan driver and driving method thereof

A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.

Oxide thin film transistor, method for fabricating TFT, array substrate for display device and method for fabricating the same

A thin film transistor substrate and a method for manufacturing the same are disclosed. The thin film transistor substrate includes a gate electrode disposed on a substrate, a gate insulating film disposed on the gate electrode, an active layer disposed on the gate insulating film and including metal oxide, a source electrode contacted with one side of the active layer and a pixel electrode contacted with the other side of the active layer; and an etch stopper interposed between the source electrode and the pixel electrode.

Growing community of inventors

Paju-si, South Korea

SangHee Yu