Samsung Electronics Co., Ltd.

Sangbom Kang

Nam-Kyu Kim

Byeongchan Lee

Keum Seok Park

Sungkwan Kang

Seungjae Lee

Si-Young Choi

Sangjin Hyun

Dongsoo Woo

Sangho Rha

Hyung-Seok Hong

Si-Hyung Lee

Ji-Young Min

Kyungseok Oh

Heedon Hwang

Shinhye Kim

Sughun Hong

HyeokJun Son

Jeong-Kyu Lee

Zulkarnain

Jungchan Lee

SungKee Han

A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Semiconductor device including MOS transistor having silicided source/drain region and method of fabricating the same

Semiconductor devices including silicide regions and methods of fabricating the same

A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material.

Method of manufacturing for semiconductor device using expandable material

A semiconductor device includes a semiconductor substrate, a gate electrode structure including a gate electrode located on an active region of the semiconductor substrate, first and second epitaxial regions located in the active region at opposite sides of the gate electrode structure, and first and second silicide layers on upper surfaces of the first and second epitaxial regions, respectively. The first and second epitaxial regions include Si&#x2014;X, where X is one of germanium and carbon, and at least a portion of each of the first and second silicide layers is devoid of X and includes Si&#x2014;Y, where Y is a metal or metal alloy.

A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.

Semiconductor device having selectively nitrided gate insulating layer and method of fabricating the same

A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

Recess gate transistor

Growing community of inventors

Seoul, South Korea

Sangbom Kang