Samsung Electronics Co., Ltd.

Sungkyunkwan University

Lg Electronics Inc.

Sang-yun Kim

Kang-yoon Lee

Sang-ho Kim

Gwan-hyung Kim

Hyung-sun Lee

Sung-hun Cho

Ho-chul Ryu

Dong-Hyun Kim

Sang-Wook Kwon

Sung-Bum Park

Jung-bae Lee

Sung-Ku Yeo

Seung-jun Lee

Young-Don Choi

Dong-Soo Lee

Sun Young Kim

Young-Ho Ryu

Bok-Yeon Won

Jae-Seok Park

Younghun Seo

Jae-hun Lee

Jonghyuk Kim

Gun-Shik Shin

Young-don Choi

Dong-In Kim

Hamed Abbasizadeh

Thi Kim Nga Truong

Seung Il Huh

Young-gie Kim

A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.

Semiconductor memory device capable of adaptively controlling bias and method of operating the same

A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n−1th connection control transistor is configured to electrically short the n−1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

Semiconductor memory devices having adjustable I/O signal line loading that supports reduced power consumption during read and write operations

An input device is provided. The input device includes a communicator for communicating with an electronic device, a pen tip provided on one end portion of the input device, an electrode part provided at a position spaced apart at a predetermined interval from the pen tip, and a processor configured to apply a predetermined frequency signal to the electrode part, and control the communicator so as to transmit, to the electronic device, the signal of which frequency changed according to a capacitance formed between the electrode part and the electronic device.

Input device including pen tip, electronic system and control method therefor

Disclosed is an input device. The input device includes a communicator configured to communicate with an electronic device, a pen tip provided at one end of the input device, a first electrode portion including a plurality of first sub-electrodes spaced apart from each other by a predetermined distance from the pen tip, a second electrode portion including a plurality of second sub-electrodes spaced apart from each other to correspond to each of the plurality of first sub-electrodes at a position spaced apart from the first electrode portion by a predetermined distance, a processor to provide a driving signal to the first electrode portion and the second electrode portion, generate tilt information of the input device on the basis of a plurality of capacitances formed between the plurality of first sub-electrodes and the plurality of second sub-electrodes, and transmit the tilt information to the electronic device.

Input device, electronic system and control method therefor

An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

Electronic device for wirelessly receiving power and method for operating the same

A block-based image denoising method includes determining similarities between a current block and reference blocks within a search range around the current block, from among certain-sized blocks divided from an input image; determining weights of the reference blocks with respect to the current block based on the similarities; and generating resultant blocks by denoising the current block with respect to every block of the input image based on the weights of the reference blocks.

Method and apparatus for block-based image denoising

A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n&#x2212;1) have an error.

Method for shifting a phase of a clock signal and memory chip using the same

Disclosed is a mobile robot charge station return system, which may return a mobile robot to a charge station exactly and rapidly according to a charge station position guidance signal emitted from the charge station. The mobile robot charge station return system includes a charge station for transmitting charge station position guidance signals to different areas in such a way that different emitting distances of the charge station position guidance signals change according to a predetermined time period; and a mobile robot for receiving the charge station position guidance signals, calculating direction and distance information, and returning to the charge station according to the calculated direction and distance information.

Mobile robot charge station return system

A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

Semiconductor memory utilizing a method of coding data

Growing community of inventors

Suwon-si, South Korea

Sang-yun Kim