Samsung Electronics Co., Ltd.

Sang-youn Jo

Bo-un Yoon

Chang-ki Hong

Hong-soo Kim

Byoung-ho Kwon

Jin-sook Choi

Se-rah Yun

Joon-Hee Lee

Jeong-Hyuk Choi

Keon-Soo Kim

Seong-Soon Cho

Dae-youp Lee

Bong-cheol Kim

Jae-Sun Yun

Seong-soo Kim

Jin-Yong Oh

Byeong-hwan Son

Ja-min Koo

Jang-hwan Jeong

In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

Semiconductor device including dummy gate part and method of fabricating the same

Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

Method of forming semiconductor device patterns

A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

Method of applying wire voltage to semiconductor device

In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.

NAND-type flash memory devices and fabrication methods thereof

Methods of forming electrically isolated active regions in semiconductor substrates include the steps of forming a plurality of trenches in a face of a semiconductor substrate to define an active region pedestal between first and second dummy region pedestals and then forming an electrically insulating layer on the active region and dummy region pedestals and in the trenches disposed therebetween. A mask is then patterned to expose a portion of the electrically insulating layer on the active region pedestal and then the exposed portion of the electrically insulating layer is etched so that a thickness of the electrically insulating layer on the active region pedestal is less than a thickness of the electrically insulating layer on the first and second dummy region pedestals. A step is then performed to planarize the electrically insulating layer to selectively expose the active region pedestal but not the first and second dummy region pedestals. This planarizing step also results in the formation of a uniform surface profile at the edges of the active region pedestal.

Methods of forming electrically isolated active region pedestals using

Growing community of inventors

Suwon-si, South Korea

Sang-youn Jo