Samsung Electronics Co., Ltd.

Sang-Youl Kwon

Jin-Young Kim

Kwang-Soo Kim

Bongyong Lee

Bong-Yong Lee

Heon-Kyu Lee

Euido Kim

Hye Yeon Yun

Haebum Lee

Houng-kuk Jang

Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

Flash memory devices with selective bit line discharge paths and methods of operating the same

A semiconductor memory device includes a main cell array region, a first redundancy cell array region and a first dummy cell array region that are formed at one side of the main cell array region, and a second redundancy cell array region and a second dummy cell array region that are formed at the other side of the main cell array region. The first redundancy cell array region includes a first redundancy bitline, and the first dummy cell array region includes first dummy bitlines. The second redundancy cell array region includes a second redundancy bitline, and the second dummy cell array region includes second dummy bitlines. The first and second redundancy cell array regions are disposed closer to the main cell array region than the first and second dummy cell array regions.

Semiconductor memory device and method for repairing the same

Growing community of inventors

Suwon-si, South Korea

Sang-Youl Kwon