Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Konkuk University Industrial Cooperation Corp

Sang Yong No

Kwi Hyun Kim

Ji Yeon Choi

Hwa Rang Lee

Sung Hoon Kim

Jang Soo Kim

Tae Ho Kang

Kyung Ho Kim

Dong Hee Shin

Sun Kwun Son

Byoung Sun Na

Kook Hyun Choi

Kwihyun Kim

Chang-Soo Lee

Kyungho Kim

Chong Chul Chai

Kyung-Ho Park

Jong-in Kim

Youn Hak Jeong

Hyuk-Jin Kim

Jong Woong Chang

Jong Hwan Lee

Gichang Lee

Jae-Jin Song

Kwan Ho Kim

Seung-hwan Kim

Hyo-Seop Kim

Gi Chang Lee

Kee Chan Park

YoungJe Cho

Shin Tack Kang

Joon Hoo Choi

Youngsoo Sohn

Seung Soo Baek

Ki Yeup Lee

Yi Kyoung You

Yongjo Kim

Bong Jun Lee

Sun Hyung Kim

Jiyeon Choi

Hwa-Rang Lee

Sang Ki Kwak

Myoung Sup Kim

A gate driving circuit includes: a first pull up control circuit for controlling a voltage of a pull up control node in response to a previous carry signal; a pull down control circuit for controlling a voltage of a pull down control node in response to the voltage of the pull up control node; a boosting circuit including a boosting capacitor and for boosting the voltage of the pull up control node; a gate output circuit for outputting a plurality of gate signals having different timings in response to the voltage of the pull up control node and the voltage of the pull down control node; and a stabilizing circuit including a control electrode connected to an end of the boosting capacitor, a first electrode for receiving a first high power voltage and a second electrode connected to the first pull up control circuit.

Gate driving circuit and display apparatus including the same

A display device includes a base layer including a display area and a non-display area, an emission unit including a first electrode electrically connected to a first driving power source, a second electrode electrically connected to a second driving power source, and a light-emitting element disposed between first and second electrodes, a first transistor including a first terminal electrically connected to the first driving power source, a second terminal electrically connected to the first electrode of the emission unit, and a gate electrode electrically connected to a first node, a second transistor including a first terminal electrically connected to a data line, a second terminal electrically connected to the first node, and a gate electrode electrically connected to a scan line, and an electrostatic discharge circuit disposed in the display area and disposed between the first driving power source and the data line.

Display device

A stage circuit includes: an output unit connected to a first power input terminal and a second power input terminal, the output unit outputting an enable output signal to a first output terminal and an enable carry signal to a second output terminal; a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal, and a second input terminal; and a second driver connected to a first input terminal, the second input terminal, the first power input terminal, and the clock input terminal, the second driver controlling a voltage of the first node. The second driver includes: a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and a control transistor and a first capacitor, connected in series between the control node and the clock input terminal.

Stage circuit and display device including the same

A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.

Display panel and display device including the same

There is provided a display device comprises a substrate; a circuit layer; and an element layer. The element layer comprises light emitting elements disposed in emission areas of a display area of the substrate, and light sensing elements disposed in light sensing areas of the display area. The circuit layer comprises light emitting pixel drivers electrically connected to the light emitting elements; light sensing pixel drivers electrically connected to the light sensing elements; data lines electrically connected to the light emitting pixel drivers; first dummy lines extending in a first direction; second dummy lines extending in parallel with the data lines; and a reset control line electrically connected to the light sensing pixel drivers, extending in the first direction, transmitting a reset control signal for resetting the light sensing pixel drivers, and overlapping at least some of the first dummy lines.

A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

A display device includes a first vertical power line extending in a first direction and receiving a first power source; and a first horizontal power line extending in a second direction intersecting the first direction between a first pixel and a second pixel and receiving the first power source, each of the first pixel and the second pixel includes first to third sub-pixels sequentially disposed in the first direction, the first pixel includes a first common pattern between the first sub-pixel and the second sub-pixel extending in the second direction, the first sub-pixel of the first pixel and the second sub-pixel of the first pixel share the first common pattern and are connected to the first vertical power line, and the third sub-pixel of the first pixel shares the first horizontal power line with the first sub-pixel of the second pixel.

Display device having sub-pixels that share a horizontal power line

A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver.

Display device and tiled display device including the same

A gate driving circuit includes: a pull-up control circuit configured to control a voltage of a pull-up control node in response to a pull-up control signal; a pull-down control circuit configured to control a voltage of a pull-down control node in response to the voltage of the pull-up control node; a carry output circuit configured to output a carry signal in response to the voltage of the pull-up control node and the voltage of the pull-down control node; and a gate output circuit configured to output a plurality of gate signals having different timings in response to the voltage of the pull-up control node and the voltage of the pull-down control node, wherein a width of the carry signal is greater than a width of each of the gate signals.

A scan signal driver includes: a plurality of stages configured to be driven by dividing a first frame period into a display period and a sensing period, and to sequentially output scan signals at the display period, wherein each of the plurality of stages comprises: an output control circuit; and a memory control circuit, wherein the scan driver is configured to: irregularly set a specific stage of the plurality of stages at a display period every frame; control the specific stage to: store a voltage by using the memory control circuit; and output a sensing signal by using the stored voltage at a sensing period, and the memory control circuit includes: a second memory transistor configured to electrically connect an M node with an I node; and a third memory transistor configured to electrically connect the output control circuit with the I node.

Scan signal driver and display device including the same

Provided herein may be a pixel. The pixel may include a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power line, and a second electrode coupled to a second node, a control transistor including a gate electrode coupled to the first node, a first electrode coupled to the second node, and a second electrode that is different from the first electrode, a first emission unit including at least one light-emitting element coupled between the second electrode of the control transistor and a second power line, and a second emission unit including at least one light-emitting element coupled between the second node and the second power line, wherein the second electrode of the control transistor is coupled to a first electrode of the first emission unit.

Pixel and display device including the same

Provided is a tiled display. The tiled display includes: a first display device including a first display area including pixels, a second display device including a second display area including pixels adjacent to the first display area, and a seam between the first display area and the second display area. Each of the first display device and the second display device includes: a first base part supporting a respective one of the first display device and the second display device, a thin-film transistor layer on the first base part, the thin-film transistor layer including thin-film transistors included in the pixels and including connection lines in the seam, and bridge electrodes in the seam to couple between the connection lines of the first display device and the second display device.

Tiled display

A display device, includes: pixels at a display area; gate lines at the display area, and connected to the pixels; carry clock lines and scan clock lines at the display area; and a gate driving circuit distributedly located at the display area, and connected to the carry clock lines, the scan clock lines, and the gate lines. The gate driving circuit includes a plurality of stages, each of the stages to output, as a carry signal, a carry clock signal supplied through a corresponding carry clock line from among the carry clock lines, and to output, as a scan signal, a scan clock signal supplied through a corresponding scan clock line from among the scan clock lines. The corresponding carry clock line and the corresponding scan clock line corresponding to one stage from among the stages are spaced from each other with at least one of the pixels interposed therebetween.

Display device having gate driving circuit stages located between pixels in the display area

A scan driver includes active stages. Each active stage includes a first transistor that resets a control node, a second transistor that transfers a previous carry signal to the control node, a third transistor that transfers a scan clock signal to a scan output node, a first capacitor electrically connected between the control node and the scan output node, a fourth transistor that transfers a first low voltage to the scan output node, a fifth transistor that transfers a carry clock signal to a carry output node, a sixth transistor that electrically connects the control node to the carry output node, and a seventh transistor that transfers a second low voltage to the control node.

Scan driver and display device

A display device includes a data driver that outputs a first data signal and a second data signal of different voltages, and a pixel that emits light in response to the first data signal and the second data signal. The pixel includes a current generator generating a driving current corresponding to the first data signal, a first light emitting part including a first electrode, a second electrode, and a first light emitting element, a second light emitting part including a third electrode, a fourth electrode connected, and a second light emitting element, and a current controller controlling a divided current supplied to the second light emitting part in response to the second data signal.

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Seoul, South Korea

Sang Yong No