Samsung Electronics Co., Ltd.

Sang-yong Kim

Chang-ki Hong

Joon-Sang Park

Kun-tack Lee

Yong-pil Han

Ji-Young Kim

Sang-jun Choi

Kyeong-Koo Chi

Jung-Min Oh

Seung-Pil Chung

Woo-Gwan Shim

Chang-jin Kang

Jeong-sic Jeon

Seung-Young Son

Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

Phase change memory elements having a confined portion of phase change material on a recessed contact

Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge insulating layer are etched to define an electrode region. The mold oxide layer is removed using an etching gas having an etch selectivity of 500 or greater for the mold oxide layer with respect to the bridge insulating layer.

Method of manufacturing capacitor of semiconductor device

Methods of fabricating phase change memory elements having a confined portion of phase change material on a recessed contact

A semiconductor memory device is provided, including a substrate and storage nodes formed on the substrate from a silicon oxide layer, the layer having been substantially removed by wet etching the silicon oxide layer to a predetermined depth of the storage nodes and dry etching the remaining portion of the silicon oxide layer to expose the storage nodes.

Storage nodes of a semiconductor memory

A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.

Semiconductor device including bit line formed using damascene technique and method of fabricating the same

A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.

Semiconductor device and method of forming the same

A method and semiconductor memory device are provided for manufacturing storage nodes using wet etching and dry etching including, when removing a silicon oxide layer including storage nodes, wet etching a portion of the silicon oxide layer using a buffered oxide etchant ('BOE') solution or a hydrogen fluoride ('HF') solution, and dry etching the remaining silicon oxide layer using a mixed gas of anhydrous HF, isopropyl alcohol (&#x201c;IPA&#x201d;) and vapor to thereby prevent short circuits caused by fallen storage nodes in the semiconductor memory device.

Method of manufacturing storage nodes of a semiconductor memory device using a two-step etching process

A method and system for transferring a wafer cassette between an Automated Guide Vehicle (AGV) and process equipment in a semiconductor fabrication facility involves transmitting a first signal from the AGV to the process equipment indicative of a cassette transfer request, checking whether the process equipment is in a suitable mode, setting the process equipment to the suitable mode after the checking step if the process equipment was not already in the suitable mode, and transferring the cassette between the AGV and the process equipment. A second transmitting step may be included, which sends a signal from the process equipment to the AGV authorizing the transfer of the cassette. The transmissions may be accomplished by wireless communications links such as a photo-coupled Parallel Input/Output link. A plurality of sensors may be used to detect whether a cassette is anywhere on a cassette stage during the checking step.

Growing community of inventors

Gyeonggi-do, South Korea

Sang-yong Kim