Hynix Semiconductor Inc.

Skhynix Inc.

Sang-Yeon Byeon

Kyung-Hoon Kim

Chang-Kyu Choi

Dae-Han Kwon

Yong-Ki Kim

Jong-Ho Kang

A semiconductor device includes a sampling unit suitable for sampling a logic value of an input signal based on an edge of an operation clock to output a sampling signal, an edge detection unit suitable for detecting an edge of the input signal based on the sampling signal, and a phase control unit suitable for controlling a phase of the operation clock while periodically changing a value of a clock delay code at each predetermined period and substituting a code value, which is obtained by calculating a value of the clock delay code corresponding to a time point at which an operation of the edge detection unit is completed and a value of a pre-phase code determined based on the sampling signal, for the clock delay code.

Semiconductor device and semiconductor system including the same

A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.

Buffer circuit

A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.

Clock data recovery circuit and method for operating the same

Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus

A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.

Semiconductor device and method for operating the same

A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.

Semiconductor memory device

A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.

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Kyoungki-do, South Korea

Sang-Yeon Byeon