Samsung Electronics Co., Ltd.

Sang-Wook Seo

Jeong-Hoon Lee

Hye-Soo Shin

Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.

Methods of dividing layouts and methods of manufacturing semiconductor devices using the same

A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout of a curved polygon type; coloring the design layout of the curved polygon type; generating stitching shapes for preventing acute corners in stitching areas of the colored design layout of the curved polygon type; separating the design layout including the stitching shapes for preventing the acute corners into separated design layouts of curved polygon type according to colors; and changing the separated design layouts of the curved polygon type to design layouts of a second polygon type.

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Seoul, South Korea

Sang-Wook Seo